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XC95144XL-10TQ144C

更新时间： 2024-01-05 20:17:06
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赛灵思 - XILINX 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
10页 93K
描述
XC95144XL High Performance CPLD

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XC95144XL-10TQ144C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP144,.87SQ,20针数：144
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：1.68Is Samacsys：N
其他特性：144 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3V最大时钟频率：81.3 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G144
JESD-609代码：e0JTAG BST：YES
长度：20 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：117
宏单元数：144端子数量：144
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 117 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：225
电源：2.5/3.3,3.3 V可编程逻辑类型：FLASH PLD
传播延迟：10 ns认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：20 mm
Base Number Matches：1

XC95144XL-10TQ144C 数据手册

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0
R
XC95144XL High Performance  
CPLD  
0
5
DS056 (v1.5) August 21, 2003  
Preliminary Product Specification  
Features  
Power Estimation  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XL device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
•
•
•
•
5 ns pin-to-pin logic delays  
System frequency up to 178 MHz  
144 macrocells with 3,200 usable gates  
Available in small footprint packages  
-
-
-
100-pin TQFP (81 user I/O pins)  
144-pin TQFP (117 user I/O pins)  
144-CSP (117 user I/O pins)  
For a general estimate of I , the following equation may be  
•
•
Optimized for high-performance 3.3V systems  
CC  
used:  
-
-
Low power operation  
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V  
signals  
I
(mA) = MC (0.175*PT + 0.345) + MC (0.052*PT  
CC  
HS HS LP LP  
+ 0.272) + 0.04 * MC  
(MC +MC )* f  
TOG  
HS  
LP  
where:  
-
-
3.3V or 2.5V output capability  
Advanced 0.35 micron feature size CMOS  
Fast FLASH™ technology  
MC = # macrocells in high-speed configuration  
HS  
PT = average number of high-speed product terms  
HS  
Advanced system features  
per macrocell  
-
-
In-system programmable  
MC = # macrocells in low power configuration  
LP  
Superior pin-locking and routability with  
Fast CONNECT™ II switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Local clock inversion with three global and one  
product-term clocks  
Individual output enable per output pin with local  
inversion  
Input hysteresis on all user and boundary-scan pin  
inputs  
PT = average number of low power product terms per  
LP  
macrocell  
f = maximum clock frequency  
MCTOG = average % of flip-flops toggling per clock  
(~12%)  
-
-
-
-
-
This calculation was derived from laboratory measurements  
of an XC9500XL part filled with 16-bit counters and allowing  
a single output (the LSB) to be enabled. The actual I  
value varies with the design application and should be veri-  
fied during normal system operation. Figure 1 shows the  
above estimation in a graphical form. For a more detailed  
discussion of power consumption in this device, see Xilinx  
application note XAPP114, “Understanding XC9500XL  
CPLD Power.”  
CC  
-
-
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
•
•
•
•
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
250  
178 MHz  
200  
-
Endurance exceeding 10,000 program/erase  
cycles  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
150  
104 MHz  
•
Pin-compatible with 5V-core XC95144 device in the  
100-pin TQFP package  
100  
50  
0
Description  
The XC95144XL is a 3.3V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of eight  
54V18 Function Blocks, providing 3,200 usable gates with  
propagation delays of 5 ns. See Figure 2 for architecture  
overview.  
100  
Clock Frequency (MHz)  
200  
50  
150  
DS056_01_121501  
Figure 1: Typical I vs. Frequency for XC95144XL  
CC  
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS056 (v1.5) August 21, 2003  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567...10

中文翻译

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XC95144XL-10TQ144C 替代型号

型号 品牌 替代类型 描述 数据表
XC95144XL-7TQG144I XILINX

完全替代

 Flash PLD, 7.5ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144
XC95144XL-7TQG144C XILINX

完全替代

 Flash PLD, 7.5ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144

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XC95144XL-10TQ144I XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-10TQG100C XILINX

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 		Flash PLD, 10ns, 144-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100
XC95144XL-10TQG144C XILINX

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 		Flash PLD, 10ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144
XC95144XL-10TQG144I XILINX

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 		Flash PLD, 10ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144
XC95144XL-5CS144C XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-5TQ100C XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-5TQ144C XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-7CS144C XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-7CS144I XILINX

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 		XC95144XL High Performance CPLD
XC95144XL-7CSG144I XILINX

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 		Flash PLD, 7.5ns, 144-Cell, CMOS, PBGA144, LEAD FREE, CSP-144

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