Datasheet > XC95144SERIES

XC95144SERIES

更新时间： 2024-02-22 19:37:46

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
9页	76K
描述
In-System Programmable CPLD

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数据手册

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XC95144SERIES 数据手册

XC95144 In-System Programmable

CPLD

December 4, 1998 (Version 4.0)

Product Specification

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Features

•

7.5 ns pin-to-pin logic delays on all pins

to 111 MHz

(mA) =

CNT

(1.7) + MC (0.9) + MC (0.006 mA/MHz) f

•

144 macrocells with 3,200 usable gates

Up to 133 user I/O pins

5 V in-system programmable

Where:

= Macrocells in high-performance mode

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

MC = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block

90 product terms drive any or all of 18 macrocells

within Function Block

Global and product term clocks, output enables, set

and reset signals

Figure 1 shows a typical calculation for the XC95144

device.

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

Programmable power reduction mode in each

macrocell

600

(480)

•

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

400

High Performance

Low Power

(320)

(300)

3.3 V or 5 V I/O capability

200

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

(160)

•

Available in 100-pin PQFP, 100-pin TQFP, and 160-pin

PQFP packages

100

Clock Frequency (MHz)

X5898B

Description

The XC95144 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of eight

36V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 7.5 ns. See Figure 2 for the architec-

ture overview.

Figure 1: Typical I_ccvs. Frequency for XC95144

Power Management

Power dissipation can be reduced in the XC95144 by con-

figuring macrocells to standard or low-power modes of

operation. Unused macrocells are turned off to minimize

power dissipation.

December 4, 1998 (Version 4.0)

12 3 4 5 6 7...9

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与XC95144SERIES相关器件

型号	品牌	获取价格	描述	数据表
XC95144XL	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10CS144C	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10CS144I	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10CSG144I	XILINX	获取价格	Flash PLD, 10ns, 144-Cell, CMOS, PBGA144, LEAD FREE, CSP-144
XC95144XL-10TQ100C	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10TQ100I	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10TQ144C	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10TQ144I	XILINX	获取价格	XC95144XL High Performance CPLD
XC95144XL-10TQG100C	XILINX	获取价格	Flash PLD, 10ns, 144-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100
XC95144XL-10TQG144C	XILINX	获取价格	Flash PLD, 10ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144

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