Datasheet > XC4005E-4CBG164M

XC4005E-4CBG164M

更新时间： 2024-11-09 06:07:35

品牌	Logo	应用领域
赛灵思 - XILINX		栅
页数	文件大小	规格书
23页	138K
描述
Field Programmable Gate Array, 196 CLBs, 3000 Gates, 111MHz, CMOS, CQFP164, CERAMIC, QFP-164

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XC4005E-4CBG164M 数据手册

XC4000E High-Reliability

Field Programmable Gate Arrays

November 21, 1997 (Version 1.3)

Product Specification

Program veriﬁcation

Internal node observability

XC4000E High-Reliability Features

•

System featured Field-Programmable Gate Arrays

•

Backward Compatible with XC4000 Devices

Development System runs on most common computer

platforms

Available in class Q fully compliant QML and Military

temperature range only

Select-RAM^TMmemory: on-chip ultra-fast RAM with

synchronous write option

dual-port RAM option

Interfaces to popular design environments

Fully automatic mapping, placement and routing

Interactive design editor for design optimization

Abundant ﬂip-ﬂops

Flexible function generators

Dedicated high-speed carry logic

Wide edge decoders on each edge

Hierarchy of interconnect lines

Internal 3-state bus capability

8 global low-skew clock or signal distribution

networks

•

Certiﬁed to MIL-PRF-38535, appendix A QML

(Qualiﬁed Manufacturers Listing)

•

System Performance beyond 60 MHz

Flexible Array Architecture

Low Power Segmented Routing Architecture

Systems-Oriented Features

Xilinx High-Reliability

XC4000E family is supplied under the following standard

microcircuit drawings (SMDs):

IEEE 1149.1-compatible boundary scan logic

support

Individually programmable output slew rate

Programmable input pull-up or pull-down resistors

12-mA sink current per XC4000E output

XC4005E 5962-97522

XC4010E 5962-97523

XC4013E 5962-97524

XC4025E 5962-97525

For more information contact DSCC (Defense Supply Cen-

ter Columbus) Columbus, Ohio.

•

Conﬁgured by Loading Binary File

Unlimited reprogrammability

Readback Capability

Table 1: XC4000E Field Programmable Gate Arrays

Max.

Logic

Gates

Typical

Max. RAM Gate Range

Max.

Decode

Inputs

Number

Bits

(Logic and

RAM)*

CLB

Total

Max.

Device

(No RAM) (No Logic)

Matrix CLBs Flip-Flops per side User I/O Packages

XC4005E

5,000

10,000

13,000

25,000

6,272

12,800

18,432

32,768

3,000 - 9,000 14 x 14

196

400

576

616

112

160

192

256

PG156,

CB164

XC4010E

XC4013E

XC4025E

7,000 - 20,000 20 x 20

1,120

1,536

2,560

PG191,

CB196

10,000 -

30,000

24 x 24

PG223,

CB228

15,000 -

45,000

32 x 32 1,024

PG299,

CB228

Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

November 21, 1997 (Version 1.3)

8-11

12 3 4 5 6 7...23

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与XC4005E-4CBG164M相关器件

型号	品牌	获取价格	描述	数据表
XC4005E-4PC84C	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PC84I	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PG156B	XILINX	获取价格	Field Programmable Gate Array, 196 CLBs, 3000 Gates, 111MHz, 196-Cell, CMOS, CPGA156, CERA
XC4005E-4PG156C	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PG156I	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PG156M	XILINX	获取价格	Field Programmable Gate Array, 196 CLBs, 3000 Gates, 111MHz, 196-Cell, CMOS, CPGA156, CERA
XC4005E-4PQ100C	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PQ100I	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PQ160C	ETC	获取价格	Field Programmable Gate Array (FPGA)
XC4005E-4PQ160I	ETC	获取价格	Field Programmable Gate Array (FPGA)

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