XC4000
Logic Cell Array Family
Product Specifications
Description
Features
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
•
Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders (four per edge)
– Hierarchy of interconnect lines
– Internal 3-state bus capability
– Eight global low-skew clock or signal distribution
network
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
The XC4000 family provides a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of program-
mable Input/Output Blocks (IOBs).
XC4000 devices have generous routing resources to ac-
commodate the most complex interconnect patterns. They
are customized by loading configuration data into the inter-
nal memory cells. The FPGA can either actively read its
configuration data out of external serial or byte-parallel
PROM (master modes), or the configuration data can be
written into the FPGA (slave and peripheral modes).
•
•
•
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
The XC4000 family is supported by powerful and sophisti-
cated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block place-
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate (2 modes)
– Programmable input pull-up or pull-down resistors
– 12-mA sink current per output
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
waremustbeadaptedtodifferentuserapplications.FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
– 24-mA sink current per output pair
•
•
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
For a detailed description of the device features, architec-
ture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
Table 1. The XC4000 Family of Field-Programmable Gate Arrays
Device
XC4003
XC4005
XC4006
XC4008 XC4010/10D XC4013
XC4020
XC4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
3,000
10 x 10
100
360
30
5,000
14 x 14
196
616
42
6,000
16 x 16
256
768
48
8,000
18 x 18
324
936
54
10,000
20 x 20
400
1,120
60
13,000
24 x 24
576
1,536
72
20,000
28 x 28
784
2,016
84
25,000
32 x 32
1,024
2,560
96
3,200
80
6,272
112
8,192
128
10,368
144
12,800*
160
18,432
192
25,088
224
32,768
256
Number of IOBs
*XC4010D has no RAM
2-47