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XC3SD1800A-5FGG676C PDF预览

XC3SD1800A-5FGG676C

更新时间： 2024-09-19 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
101页 2496K
描述
Field Programmable Gate Array, 4160 CLBs, 1800000 Gates, 280MHz, 37440-Cell, CMOS, PBGA676, LEAD FREE, FBGA-676

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XC3SD1800A-5FGG676C 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LEAD FREE, FBGA-676针数：676
Reach Compliance Code：compliantECCN代码：3A991.D
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.28最大时钟频率：280 MHz
JESD-30 代码：S-PBGA-B676JESD-609代码：e1
长度：27 mm湿度敏感等级：3
可配置逻辑块数量：4160等效关口数量：1800000
输入次数：519逻辑单元数量：37440
输出次数：409端子数量：676
最高工作温度：85 °C最低工作温度：
组织：4160 CLBS, 1800000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA676,26X26,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：250电源：1.2,2.5/3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.6 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：27 mm
Base Number Matches：1

XC3SD1800A-5FGG676C 数据手册

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1
Spartan-3A DSP FPGA Family Data Sheet  
DS610 October 4, 2010  
Product Specification  
Module 1:  
Introduction and Ordering Information  
DS610 (v3.0) October 4, 2010  
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Introduction  
Features  
Architectural Overview  
Configuration Overview  
General I/O Capabilities  
Supported Packages and Package Marking  
Ordering Information  
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UG431: XtremeDSP™ DSP48A for Spartan-3A DSP  
FPGAs User Guide  
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DSP48A Slice Design Considerations  
DSP48A Architecture Highlights  
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18 x 18-Bit Multipliers  
48-Bit Accumulator  
18-bit Pre-Adder  
•
DSP48A Application Examples  
Module 2:  
Functional Description  
DS610 (v3.0) October 4, 2010  
Module 3:  
DC and Switching Characteristics  
DS610 (v3.0) October 4, 2010  
The functionality of the Spartan®-3A DSP FPGA family is  
described in the following documents.  
•
DC Electrical Characteristics  
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UG331: Spartan-3 Generation FPGA User Guide  
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•
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Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
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Clocking Resources  
Digital Clock Managers (DCMs)  
Block RAM  
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Switching Characteristics  
Configurable Logic Blocks (CLBs)  
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I/O Timing  
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Distributed RAM  
SRL16 Shift Registers  
Carry and Arithmetic Logic  
Configurable Logic Block (CLB) Timing  
Digital Clock Manager (DCM) Timing  
Block RAM Timing  
XtremeDSP Slice Timing  
Configuration and JTAG Timing  
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I/O Resources  
Programmable Interconnect  
ISE® Software Design Tools and IP Cores  
Embedded Processing and Control Solutions  
Pin Types and Package Overview  
Package Drawings  
Module 4:  
Pinout Descriptions  
DS610 (v3.0) October 4, 2010  
Powering FPGAs  
Power Management  
•
•
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Pin Descriptions  
Package Overview  
Pinout Tables  
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UG332: Spartan-3 Generation Configuration User Guide  
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Configuration Overview  
Configuration Pins and Behavior  
Bitstream Sizes  
Footprint Diagrams  
Detailed Descriptions by Mode  
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Master Serial Mode using Platform Flash PROM  
Master SPI Mode using Commodity Serial Flash  
Master BPI Mode using Commodity Parallel Flash  
Slave Parallel (SelectMAP) using a Processor  
Slave Serial using a Processor  
JTAG Mode  
•
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ISE iMPACT Programming Examples  
MultiBoot Reconfiguration  
Design Authentication using Device DNA  
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS610 October 4, 2010  
www.xilinx.com  
Product Specification  
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XC3SD1800A-5FGG676C 替代型号

型号 品牌 替代类型 描述 数据表
XC3SD1800A-4FGG676I XILINX

完全替代

 Field Programmable Gate Array, 4160 CLBs, 1800000 Gates, 250MHz, 37440-Cell, CMOS, PBGA676
XC3SD1800A-4FGG676C XILINX

完全替代

 Field Programmable Gate Array, 4160 CLBs, 1800000 Gates, 250MHz, 37440-Cell, CMOS, PBGA676
XC3SD1800A-4FG676I XILINX

完全替代

 Field Programmable Gate Array, 4160 CLBs, 1800000 Gates, 250MHz, 37440-Cell, CMOS, PBGA676

与XC3SD1800A-5FGG676C相关器件

型号 品牌 获取价格 描述 数据表
XC3SD3400A-4CS484C XILINX

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 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-4CS484I XILINX

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 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-4CS484LI XILINX

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 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-4CSG484C XILINX

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 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-4CSG484LI XILINX

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 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-4FG676C XILINX

获取价格

 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA676
XC3SD3400A-4FGG676C XILINX

获取价格

 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA676
XC3SD3400A-4FGG676I XILINX

获取价格

 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 250MHz, 53712-Cell, CMOS, PBGA676
XC3SD3400A-5CS484C XILINX

获取价格

 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 280MHz, 53712-Cell, CMOS, PBGA484
XC3SD3400A-5CSG484C XILINX

获取价格

 		Field Programmable Gate Array, 5968 CLBs, 3400000 Gates, 280MHz, 53712-Cell, CMOS, PBGA484

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