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Spartan-II 2.5V FPGA
R
Automotive IQ Product Family:
Introduction and Ordering
Product Specification
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DS105-1 (v2.0) August 9, 2013
Introduction
The Spartan™-II 2.5V Field-Programmable Gate Array
(FPGA) Automotive IQ product family gives users high per-
formance, abundant logic resources, and a rich feature set.
The six-member family offers densities ranging from 15,000
to 200,000 system gates, as shown in Table 1.
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System level features
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SelectRAM+™ hierarchical memory:
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·
·
16 bits/LUT distributed RAM
Configurable 4K-bit block RAM
Fast interfaces to external RAM
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Fully PCI compliant
Spartan-II devices deliver more gates, I/Os, and features
per Dollar/Euro than other FPGAs by combining advanced
0.18 μm process technology with a streamlined
Virtex™-based architecture. Features include block RAM
(to 56K bits), distributed RAM (to 75,264 bits), 16 selectable
I/O standards, and four DLLs. Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
The Spartan-II family is a superior alternative to mask-pro-
grammed ASICs. The FPGA avoids the initial cost, lengthy
development cycles, and inherent risk of conventional
ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement neces-
sary (impossible with ASICs).
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Versatile I/O and packaging
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Family footprint compatibility in common packages
16 high-performance interface standards
Zero hold time simplifies system timing
Fully supported by powerful Xilinx development system
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Foundation™ ISE Series: Fully integrated software
Alliance Series™: For use with third-party tools
Fully automatic mapping, placement, and routing
Features
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Guaranteed to meet full electrical specifications over
T = –40°C to +125°C
J
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Refer to Spartan-II 2.5V FPGA Detailed Functional
Description (DS001-2) for device functional description
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Second generation ASIC replacement technology
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Densities as high as 5,292 logic cells with up to
200,000 system gates
Other than the DC parameters listed, all other DC
specifications are the same as referenced in the
Spartan-II 2.5V FPGA DC and Switching
Characteristics (DS001-3) data sheet
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Streamlined features based on Virtex architecture
Unlimited reprogrammability
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Refer to Spartan-II 2.5V FPGA Pinout Tables
(DS001-4) for all pin descriptions
Table 1: Spartan-II FPGA Family Members
CLB
Array
(R x C)
Maximum
Total
Total
Logic
Cells
System Gates
(Logic and RAM)
Total
Available
Distributed RAM Block RAM
(1)
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
CLBs User I/O
Bits
Bits
16K
24K
32K
40K
48K
56K
432
15,000
30,000
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
96
216
384
600
864
1,176
86
6,144
972
132
176
176
176
284
13,824
24,576
38,400
55,296
75,264
1,728
2,700
3,888
5,292
50,000
100,000
150,000
200,000
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS105-1 (v2.0) August 9, 2013
www.xilinx.com
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Product Specification
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