16.0-30.0 GHz GaAs MMIC
Buffer Amplifier
June 2007 - Rev 12-Jun-07
B1004-BD
App Note [1] Biasing - As shown in the bonding diagram, this device can be operated with all three stages in parallel, and can be biased for
low noise performance or high power performance. Low noise bias is nominally Vd=4V, Id=90mA. More controlled performance will be
obtained by separately biasing Vd1 and Vd2 each at 4.0V, 45mA. Power bias may be as high as Vd=6.0V, Id=180mA with all stages in parallel,
or most controlled performance will be obtained by separately biasing Vd1 and Vd2 each at 6.0V, 90mA. It is also recommended to use active
biasing to keep the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the
supply voltage available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational
amplifier, with a low value resistor in series with the drain supply used to sense the current.The gate of the pHEMT is controlled to maintain
correct drain current and thus drain voltage.The typical gate voltage needed to do this is -0.3V.Typically the gate is protected with Silicon
diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is available before applying
the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pf) can be combined.The suggested configuration is to connect Vd1,2 and Vg1c,2c. Additional DC bypass capacitance
(~0.01 uF) is also recommended to all DC or combination (if gate or drains are tied together) of DC bias pads.
For Individual Stage Bias (Low Input Drive applications only) -- Each DC pad (Vd1,2 and Vg1a,2a,2b) needs to have DC bypass capacitance
(~100-200 pf) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
For Individual Stage Bias (High Input Drive applications only) -- Each DC pad (Vd1,2 and Vg1c,2c) needs to have DC bypass capacitance
(~100-200 pf) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
MTTFTables
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Channel
Rth
MTTF Hours
FITs
Temperature
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
83.4 deg Celsius
105.5 deg Celsius
127.4 deg Celsius
78.8° C/W
84.7° C/W
90.0° C/W
5.36E+10
3.52E+09
3.20E+08
1.87E-02
2.84E-01
3.13E+00
Bias Conditions: Vd1=Vd2=4.0V, Id1=45 mA, Id2=45 mA
Backplate
Channel
Rth
MTTF Hours
FITs
Temperature
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
108.3 deg Celsius
132.1 deg Celsius
155.5 deg Celsius
76.1° C/W
81.5° C/W
86.4° C/W
2.56E+09
1.99E+08
2.12E+07
3.91E-01
5.04E+00
4.72E+01
Bias Conditions: Vd1=Vd2=5.0V, Id1=70 mA, Id2=70 mA
Backplate
Channel
Rth
MTTF Hours
FITs
Temperature
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
138.1 deg Celsius
163.7 deg Celsius
188.8 deg Celsius
77.0° C/W
82.1° C/W
86.8° C/W
1.08E+08
1.02E+07
1.29E+06
9.22E+00
9.82E+01
7.73E+02
Bias Conditions: Vd1=Vd2=6.0V, Id1=90 mA, Id2=90 mA
Page 8 of 10
Mimix Broadband, Inc., 10795 Rockley Rd., Houston,Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
their obligation to be compliant with U.S. Export Laws.
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