54
R
XA Spartan-3A DSP Automotive
FPGA Family Data Sheet
DS705 (v1.1) January 20, 2009
Product Specification
Summary
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Integrated adder for complex multiply or multiply-add operation
Integrated 18-bit pre-adder
Optional cascaded Multiply or MAC
The Xilinx Automotive (XA) Spartan®-3A DSP family of FPGAs
solves the design challenges in most high-volume, cost-sensitive,
high-performance DSP automotive applications. The two-member
family offers densities ranging from 1.8 to 3.4 million system gates,
as shown in Table 1.
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Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend and Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
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Up to 519 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot-swap compliance
622+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with
integrated differential termination resistors
Introduction
XA devices are available in both extended-temperature Q-Grade
(–40°C to +125°C TJ) and I-Grade (–40°C to +100°C TJ) and are
qualified to the industry recognized AEC-Q100 standard.
The XA Spartan-3A DSP family builds on the success of the earlier
XA Spartan-3E and XA Spartan-3 FPGA families by adding
hardened DSP MACs with pre-adders, significantly increasing the
throughput and performance of this low-cost family. These XA
Spartan-3A DSP family enhancements, combined with proven
90 nm process technology, deliver more functionality and
bandwidth per dollar than ever before, setting the new standard in
the programmable logic industry.
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Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 266 Mb/s
Fully compliant 32-bit, 33 MHz PCI® technology support
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Abundant, flexible logic resources
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Densities up to 53,712 logic cells, including optional shift register
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
Because of their exceptionally low cost, XA Spartan-3A DSP
FPGAs are ideally suited to a wide range of automotive electronics
applications, including infotainment, driver information, and driver
assistance modules.
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Up to 2,268 Kbits of fast block RAM with byte write enables for
processor applications
Up to 373 Kbits of efficient distributed RAM
Registered outputs on the block RAM with operation of at least
280 MHz in the standard -4 speed grade
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Eight Digital Clock Managers (DCMs)
The XA Spartan-3A DSP family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial mask set costs
and lengthy development cycles, while also permitting design
upgrades in the field with no hardware replacement necessary
because of its inherent programmability, an impossibility with
conventional ASICs and ASSPs with their inflexible architecture.
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Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
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Eight low-skew global clock networks, eight additional clocks
per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Unique Device DNA identifier for design authentication
Features
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Very low cost, high-performance DSP solution for high-
volume, cost-conscious applications
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Complete Xilinx ISE® and WebPACK™ software support plus
Spartan-3A DSP FPGA Starter Kit
MicroBlaze™ and PicoBlaze™ embedded processor cores
BGA packaging, Pb-free only
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250 MHz DSP48A slices using XtremeDSP™ solution
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Dedicated 18-bit by 18-bit multiplier
Available pipeline stages for enhanced performance of at least
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250 MHz in the standard -4 speed grade
Common footprints support easy density migration
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48-bit accumulator for multiply-accumulate (MAC) operation
Table 1: Summary of XA Spartan-3A DSP FPGA Attributes
CLB Array (One CLB = Four Slices)
Distributed
RAM
Block
RAM
Maximum
Differential
I/O Pairs
System Equivalent
Device
Maximum
User I/O
DSP48As DCMs
Total
Total
Gates Logic Cells
1
1
)
)
Bits(
Bits(
Rows Columns
CLBs
Slices
XA3SD1800A 1800K
XA3SD3400A 3400K
37,440
53,712
88
104
48
58
4,160
5,968
16,640
23,872
260K
373K
1512K
2268K
84
126
8
8
519
469
227
213
Notes: 1. By convention, one Kb is equivalent to 1,024 bits.
© 2008–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
1
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