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XA3SD3400A-4CSG484I PDF预览

XA3SD3400A-4CSG484I

更新时间： 2024-11-08 19:57:03
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
58页 1801K
描述
Field Programmable Gate Array, 5968 CLBs, 53712 Gates, 667MHz, 53712-Cell, CMOS, PBGA484, LEAD FREE, CSBGA-484

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XA3SD3400A-4CSG484I 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LEAD FREE, CSBGA-484
针数：484Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8最大时钟频率：667 MHz
JESD-30 代码：S-PBGA-B484JESD-609代码：e1
长度：19 mm湿度敏感等级：3
可配置逻辑块数量：5968等效关口数量：53712
输入次数：309逻辑单元数量：53712
输出次数：249端子数量：484
组织：5968 CLBS, 53712 GATES封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA484,22X22,32
封装形状：SQUARE封装形式：GRID ARRAY, FINE PITCH
电源：1.2,1.2/3.3,2.5/3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.8 mm子类别：Field Programmable Gate Arrays
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：19 mmBase Number Matches：1

XA3SD3400A-4CSG484I 数据手册

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58  
XA Spartan-3A DSP Automotive  
FPGA Family Data Sheet  
DS705 (v2.0) April 18, 2011  
Product Specification  
Summary  
The Xilinx Automotive (XA) Spartan®-3A DSP family of  
FPGAs solves the design challenges in most high-volume,  
cost-sensitive, high-performance DSP automotive  
applications. The two-member family offers densities  
ranging from 1.8 to 3.4 million system gates, as shown in  
Table 1.  
•
•
•
Dual-range V  
supply simplifies 3.3V-only design  
CCAUX  
Suspend and Hibernate modes reduce system power  
Multi-voltage, multi-standard SelectIO™ interface pins  
•
•
•
•
•
•
•
•
Up to 519 I/O pins or 227 differential signal pairs  
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O  
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling  
Selectable output drive, up to 24 mA per pin  
QUIETIO standard reduces I/O switching noise  
Full 3.3V ± 10% compatibility and hot-swap compliance  
622+ Mb/s data transfer rate per differential I/O  
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O  
with integrated differential termination resistors  
Enhanced Double Data Rate (DDR) support  
DDR/DDR2 SDRAM support up to 266 Mb/s  
Fully compliant 32-bit, 33 MHz PCI® technology support  
Introduction  
XA devices are available in both extended-temperature  
Q-Grade (–40°C to +125°C T ) and I-Grade (–40°C to  
J
+100°C T ) and are qualified to the industry recognized  
J
AEC-Q100 standard.  
•
•
•
The XA Spartan-3A DSP family builds on the success of the  
earlier XA Spartan-3E and XA Spartan-3 FPGA families by  
adding hardened DSP MACs with pre-adders, significantly  
increasing the throughput and performance of this low-cost  
family. These XA Spartan-3A DSP family enhancements,  
combined with proven 90 nm process technology, deliver  
more functionality and bandwidth per dollar than ever  
before, setting the new standard in the programmable logic  
industry.  
Because of their exceptionally low cost,  
XA Spartan-3A DSP FPGAs are ideally suited to a wide  
range of automotive electronics applications, including  
infotainment, driver information, and driver assistance  
modules.  
•
•
•
Abundant, flexible logic resources  
•
Densities up to 53,712 logic cells, including optional shift  
register  
•
•
•
Efficient wide multiplexers, wide logic  
Fast look-ahead carry logic  
IEEE 1149.1/1532 JTAG programming/debug port  
Hierarchical SelectRAM™ memory architecture  
•
Up to 2,268 Kbits of fast block RAM with byte write  
enables for processor applications  
•
•
Up to 373 Kbits of efficient distributed RAM  
Registered outputs on the block RAM with operation of at  
least 280 MHz in the standard -4 speed grade  
The XA Spartan-3A DSP family is a superior alternative to  
mask programmed ASICs. FPGAs avoid the high initial  
mask set costs and lengthy development cycles, while also  
permitting design upgrades in the field with no hardware  
replacement necessary because of its inherent  
Eight Digital Clock Managers (DCMs)  
•
•
•
•
Clock skew elimination (delay locked loop)  
Frequency synthesis, multiplication, division  
High-resolution phase shifting  
Wide frequency range (5 MHz to over 320 MHz)  
programmability, an impossibility with conventional ASICs  
and ASSPs with their inflexible architecture.  
•
•
Eight low-skew global clock networks, eight additional  
clocks per half device, plus abundant low-skew routing  
Configuration interface to industry-standard PROMs  
Features  
•
•
•
Low-cost, space-saving SPI serial Flash PROM  
x8 or x8/x16 parallel NOR Flash PROM  
Unique Device DNA identifier for design authentication  
•
Very low cost, high-performance DSP solution for  
high-volume, cost-conscious applications  
•
250 MHz DSP48A slices using XtremeDSP™ solution  
•
•
•
Complete Xilinx ISE® and WebPACK™ software  
support plus Spartan-3A DSP FPGA Starter Kit  
•
•
Dedicated 18-bit by 18-bit multiplier  
Available pipeline stages for enhanced performance of at  
least 250 MHz in the standard -4 speed grade  
48-bit accumulator for multiply-accumulate (MAC)  
operation  
MicroBlaze™ and PicoBlaze™ embedded processor  
cores  
•
•
BGA packaging, Pb-free only  
Integrated adder for complex multiply or multiply-add  
operation  
•
Common footprints support easy density migration  
•
•
Integrated 18-bit pre-adder  
Optional cascaded Multiply or MAC  
© Copyright 2008–2011 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the  
United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.  
DS705 (v2.0) April 18, 2011  
www.xilinx.com  
Product Specification  
1
 
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