Datasheet > X5001PIZ

X5001PIZ

更新时间： 2024-11-26 02:57:39

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
20页	789K
描述
CPU Supervisor

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中文翻译

获取价格

数据手册

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X5001PIZ 数据手册

DATASHEET

X5001

CPU Supervisor

FN8125

Rev 1.00

May 30, 2006

FEATURES

DESCRIPTION

• 200ms power-on reset delay

This device combines three popular functions, Power-

on Reset, Watchdog Timer, and Supply Voltage

Supervision in one package. This combination lowers

system cost, reduces board space requirements, and

increases reliability.

• Low V detection and reset assertion

—Five standard reset threshold voltages

—Adjust low V reset threshold voltage using

special programming sequence

—Reset signal valid to V = 1V

• Selectable nonvolatile watchdog timer

—0.2, 0.6, 1.4 seconds

The watchdog timer provides an independent protec-

tion mechanism for microcontrollers. During a system

failure, the device will respond with a RESET signal

after a selectable time out interval. The user selects the

interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

—Off selection

—Select settings through software

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<1µA max standby current, watchdog off

• 2.7V to 5.5V operation

The user’s system is protected from low voltage condi-

tions by the device’s low V detection circuitry. When

• SPI mode 0 interface

falls below the minimum V trip point, the system

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Watchdog change latch

• High reliability

• Available packages

—8 Ld TSSOP

—8 Ld SOIC

—8 Ld PDIP

is reset. RESET is asserted until V returns to proper

operating levels and stabilizes. Five industry standard

thresholds are available, however, Intersil’s

TRIP

unique circuits allow the threshold to be reprogrammed

to meet custom requirements or to fine-tune the thresh-

old for applications requiring higher precision.

™

The device utilizes Intersil’s proprietary Direct Write

cell for the watchdog timer control bits and the V

TRIP

• Pb-free plus anneal available (RoHS compliant)

storage element, providing a minimum endurance of

100,000 write cycles and a minimum data retention of

100 years.

BLOCK DIAGRAM

RESET

Watchdog

Transition

Detector

Watchdog

Timer

Data

Reset &

Watchdog

Timebase

Command

Decode &

Control

SCK

CS/WDI

Logic

Power-on/

Low Voltage

REset

V_CC

Generation

TRIP

FN8125 Rev 1.00

May 30, 2006

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