Datasheet > X5001PZ-2.7A

X5001PZ-2.7A

更新时间： 2024-11-25 02:54:59

品牌	Logo	应用领域
英特矽尔 - INTERSIL		光电二极管监控
页数	文件大小	规格书
20页	305K
描述
CPU Supervisor

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中文翻译

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数据手册

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X5001PZ-2.7A 数据手册

X5001

Data Sheet

May 30, 2006

FN8125.1

DESCRIPTION

CPU Supervisor

This device combines three popular functions, Power-

on Reset, Watchdog Timer, and Supply Voltage

Supervision in one package. This combination lowers

system cost, reduces board space requirements, and

increases reliability.

FEATURES

• 200ms power-on reset delay

• Low V detection and reset assertion

—Five standard reset threshold voltages

—Adjust low V reset threshold voltage using

The watchdog timer provides an independent protec-

tion mechanism for microcontrollers. During a system

failure, the device will respond with a RESET signal

after a selectable time out interval. The user selects the

interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

special programming sequence

—Reset signal valid to V = 1V

• Selectable nonvolatile watchdog timer

—0.2, 0.6, 1.4 seconds

—Off selection

—Select settings through software

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<1µA max standby current, watchdog off

• 2.7V to 5.5V operation

The user’s system is protected from low voltage condi-

tions by the device’s low V detection circuitry. When

falls below the minimum V trip point, the system

is reset. RESET is asserted until V returns to proper

• SPI mode 0 interface

operating levels and stabilizes. Five industry standard

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Watchdog change latch

thresholds are available, however, Intersil’s

TRIP

unique circuits allow the threshold to be reprogrammed

to meet custom requirements or to fine-tune the thresh-

old for applications requiring higher precision.

• High reliability

• Available packages

—8 Ld TSSOP

—8 Ld SOIC

—8 Ld PDIP

™

The device utilizes Intersil’s proprietary Direct Write

cell for the watchdog timer control bits and the V

TRIP

storage element, providing a minimum endurance of

100,000 write cycles and a minimum data retention of

100 years.

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

RESET

Watchdog

Transition

Detector

Watchdog

Timer

Data

Reset &

Watchdog

Timebase

Command

Decode &

Control

SCK

CS/WDI

Logic

Power-on/

Low Voltage

REset

V_CC

Generation

TRIP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7...20

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