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X28HC256JM-15T1 PDF预览

X28HC256JM-15T1

更新时间: 2024-11-23 20:56:47
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
17页 491K
描述
32KX8 EEPROM 5V, 150ns, PQCC32, PLASTIC, MS-016AE, LCC-32

X28HC256JM-15T1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.51
风险等级:5.69Is Samacsys:N
最长访问时间:150 ns其他特性:100000 ENDURANCE WRITE CYCLES; 100 YEARS DATA RETENTION
命令用户界面:NO数据轮询:YES
数据保留时间-最小值:100耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
长度:13.97 mm内存密度:262144 bit
内存集成电路类型:EEPROM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
页面大小:128 words并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:3.55 mm最大待机电流:0.0005 A
子类别:EEPROMs最大压摆率:0.06 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:YES
宽度:11.43 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

X28HC256JM-15T1 数据手册

 浏览型号X28HC256JM-15T1的Datasheet PDF文件第2页浏览型号X28HC256JM-15T1的Datasheet PDF文件第3页浏览型号X28HC256JM-15T1的Datasheet PDF文件第4页浏览型号X28HC256JM-15T1的Datasheet PDF文件第5页浏览型号X28HC256JM-15T1的Datasheet PDF文件第6页浏览型号X28HC256JM-15T1的Datasheet PDF文件第7页 
X28HC256  
256k, 32k x 8-Bit  
Data Sheet  
September 21, 2011  
FN8108.3  
5V, Byte Alterable EEPROM  
Features  
The X28HC256 is a second generation high performance  
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s  
proprietary, textured poly floating gate technology, providing  
a highly reliable 5V only nonvolatile memory.  
• Access time: 70ns  
• Simple byte and page write  
- Single 5V supply  
- No external high voltages or VP-P control circuits  
- Self-timed  
The X28HC256 supports a 128-byte page write operation,  
effectively providing a 24µs/byte write cycle, and enabling  
the entire memory to be typically rewritten in less than 0.8  
seconds. The X28HC256 also features DATA Polling and  
Toggle Bit Polling, two methods of providing early end of  
write detection. The X28HC256 also supports the JEDEC  
standard Software Data Protection feature for protecting  
against inadvertent writes during power-up and power-down.  
- No erase before write  
- No complex programming algorithms  
- No overerase problem  
• Low power CMOS  
- Active: 60mA  
- Standby: 500µA  
Endurance for the X28HC256 is specified as a minimum  
1,000,000 write cycles per byte and an inherent data  
retention of 100 years.  
• Software data protection  
- Protects data against system level inadvertent writes  
• High speed page write capability  
• Highly reliable Direct Writecell  
- Endurance: 1,000,000 cycles  
- Data retention: 100 years  
• Early end of write detection  
- DATA polling  
- Toggle bit polling  
• Pb-free available (RoHS compliant)  
Block Diagram  
256kBIT  
EEPROM  
ARRAY  
X BUFFERS  
LATCHES AND  
DECODER  
A
TO A  
14  
0
ADDRESS  
INPUTS  
I/O BUFFERS  
Y BUFFERS  
LATCHES AND  
DECODER  
AND LATCHES  
I/O TO I/O  
0
7
DATA INPUTS/OUTPUTS  
CE  
CONTROL  
LOGIC AND  
TIMING  
OE  
WE  
V
CC  
SS  
V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2005-2007, 2010, 2011. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
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