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X28HC256JM-90T1 PDF预览

X28HC256JM-90T1

更新时间: 2024-11-23 14:45:39
品牌 Logo 应用领域
XICOR 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
23页 190K
描述
EEPROM, 32KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32

X28HC256JM-90T1 技术参数

生命周期:Transferred包装说明:QCCJ,
Reach Compliance Code:unknown风险等级:5.63
最长访问时间:90 ns其他特性:100000 ENDURANCE WRITE CYCLES; 100 YEARS DATA RETENTION
数据保留时间-最小值:100耐久性:100000 Write/Erase Cycles
JESD-30 代码:R-PQCC-J32长度:13.97 mm
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL编程电压:5 V
认证状态:Not Qualified座面最大高度:3.56 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.43 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

X28HC256JM-90T1 数据手册

 浏览型号X28HC256JM-90T1的Datasheet PDF文件第2页浏览型号X28HC256JM-90T1的Datasheet PDF文件第3页浏览型号X28HC256JM-90T1的Datasheet PDF文件第4页浏览型号X28HC256JM-90T1的Datasheet PDF文件第5页浏览型号X28HC256JM-90T1的Datasheet PDF文件第6页浏览型号X28HC256JM-90T1的Datasheet PDF文件第7页 
256K  
32K x 8 Bit  
X28HC256  
5 Volt, Byte Alterable EEPROM  
FEATURES  
DESCRIPTION  
• Access time: 70ns  
• Simple byte and page write  
—Single 5V supply  
No external high voltages or V control circuits  
—Self-timed  
The X28HC256 is a second generation high perfor-  
mance CMOS 32K x 8 EEPROM. It is fabricated with  
Xicor’s proprietary, textured poly floating gate technol-  
ogy, providing a highly reliable 5 Volt only nonvolatile  
memory.  
PP  
—No erase before write  
—No complex programming algorithms  
—No overerase problem  
• Low power CMOS  
—Active: 60mA  
—Standby: 500µA  
• Software data protection  
—Protects data against system level inadvertent  
writes  
• High speed page write capability  
• Highly reliable Direct Writecell  
—Endurance: 1,000,000 cycles  
—Data retention: 100 years  
• Early end of write detection  
DATA polling  
The X28HC256 supports a 128-byte page write opera-  
tion, effectively providing a 24µs/byte write cycle, and  
enabling the entire memory to be typically rewritten in  
less than 0.8 seconds. The X28HC256 also features  
DATA Polling and Toggle Bit Polling, two methods of  
providing early end of write detection. The X28HC256  
also supports the JEDEC standard Software Data Pro-  
tection feature for protecting against inadvertent writes  
during power-up and power-down.  
Endurance for the X28HC256 is specified as a mini-  
mum 1,000,000 write cycles per byte and an inherent  
data retention of 100 years.  
Toggle bit polling  
BLOCK DIAGRAM  
256Kbit  
EEPROM  
Array  
X Buffers  
Latches and  
Decoder  
A –A  
0
14  
Address  
Inputs  
I/O Buffers  
and Latches  
Y Buffers  
Latches and  
DECODER  
I/O –I/O  
0
7
Data Inputs/Outputs  
CE  
OE  
WE  
Control  
Logic and  
Timing  
V
CC  
SS  
V
Characteristics subject to change without notice. 1 of 23  
REV 1.1 2/1/01  
www.xicor.com  

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