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X28HC256JZ-15T13 PDF预览

X28HC256JZ-15T13

更新时间: 2023-02-26 13:28:44
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 496K
描述
EEPROM 5V

X28HC256JZ-15T13 数据手册

 浏览型号X28HC256JZ-15T13的Datasheet PDF文件第2页浏览型号X28HC256JZ-15T13的Datasheet PDF文件第3页浏览型号X28HC256JZ-15T13的Datasheet PDF文件第4页浏览型号X28HC256JZ-15T13的Datasheet PDF文件第5页浏览型号X28HC256JZ-15T13的Datasheet PDF文件第6页浏览型号X28HC256JZ-15T13的Datasheet PDF文件第7页 
DATASHEET  
256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM  
X28HC256  
Features  
The X28HC256 is a second generation high performance  
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s  
proprietary, textured poly floating gate technology, providing a  
highly reliable 5V only nonvolatile memory.  
• Access time: 90ns  
• Simple byte and page write  
- Single 5V supply  
- No external high voltages or VP-P control circuits  
- Self timed  
The X28HC256 supports a 128-byte page write operation,  
effectively providing a 24µs/byte write cycle, and enabling the  
entire memory to be typically rewritten in less than 0.8s. The  
X28HC256 also features DATA polling and Toggle bit polling,  
two methods of providing early end of write detection. The  
X28HC256 also supports the JEDEC standard software data  
protection feature for protecting against inadvertent writes  
during power-up and power-down.  
- No erase before write  
- No complex programming algorithms  
- No overerase problem  
• Low power CMOS  
- Active: 60mA  
- Standby: 500µA  
Endurance for the X28HC256 is specified as a minimum  
100,000 write cycles per byte and an inherent data retention  
of 100 years.  
• Software data protection  
- Protects data against system level inadvertent writes  
• High speed page write capability  
• Highly reliable Direct Writecell  
- Endurance: 100,000 cycles  
- Data retention: 100 years  
• Early end of write detection  
- DATA polling  
- Toggle bit polling  
• RoHS compliant  
256k BIT  
EEPROM  
ARRAY  
X BUFFERS  
LATCHES AND  
DECODER  
A
TO A  
14  
0
ADDRESS  
INPUTS  
I/O BUFFERS  
AND LATCHES  
Y BUFFERS  
LATCHES AND  
DECODER  
I/O TO I/O  
0
7
DATA INPUTS/OUTPUTS  
CE  
CONTROL  
LOGIC AND  
TIMING  
OE  
WE  
V
V
CC  
SS  
FIGURE 1. BLOCK DIAGRAM  
August 27, 2015  
FN8108.5  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2007, 2010, 2011, 2015. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  

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