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X28HC256JI-90

更新时间: 2024-02-17 02:07:46
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 301K
描述
5 Volt, Byte Alterable EEPROM

X28HC256JI-90 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:compliant风险等级:5.63
内存集成电路类型:EEPROM编程电压:5 V
Base Number Matches:1

X28HC256JI-90 数据手册

 浏览型号X28HC256JI-90的Datasheet PDF文件第2页浏览型号X28HC256JI-90的Datasheet PDF文件第3页浏览型号X28HC256JI-90的Datasheet PDF文件第4页浏览型号X28HC256JI-90的Datasheet PDF文件第5页浏览型号X28HC256JI-90的Datasheet PDF文件第6页浏览型号X28HC256JI-90的Datasheet PDF文件第7页 
X28HC256  
®
256K, 32K x 8 Bit  
Data Sheet  
June 1, 2005  
FN8108.0  
DESCRIPTION  
5 Volt, Byte Alterable EEPROM  
The X28HC256 is a second generation high perfor-  
mance CMOS 32K x 8 EEPROM. It is fabricated with  
Intersil’s proprietary, textured poly floating gate tech-  
nology, providing a highly reliable 5 Volt only nonvola-  
tile memory.  
FEATURES  
• Access time: 70ns  
• Simple byte and page write  
—Single 5V supply  
No external high voltages or V control circuits  
—Self-timed  
—No erase before write  
—No complex programming algorithms  
—No overerase problem  
• Low power CMOS  
—Active: 60mA  
—Standby: 500µA  
• Software data protection  
—Protects data against system level inadvertent  
writes  
PP  
The X28HC256 supports a 128-byte page write opera-  
tion, effectively providing a 24µs/byte write cycle, and  
enabling the entire memory to be typically rewritten in  
less than 0.8 seconds. The X28HC256 also features  
DATA Polling and Toggle Bit Polling, two methods of  
providing early end of write detection. The X28HC256  
also supports the JEDEC standard Software Data Pro-  
tection feature for protecting against inadvertent writes  
during power-up and power-down.  
Endurance for the X28HC256 is specified as a mini-  
mum 1,000,000 write cycles per byte and an inherent  
data retention of 100 years.  
• High speed page write capability  
• Highly reliable Direct Write cell  
—Endurance: 1,000,000 cycles  
—Data retention: 100 years  
• Early end of write detection  
—DATA polling  
—Toggle bit polling  
BLOCK DIAGRAM  
256Kbit  
EEPROM  
Array  
X Buffers  
Latches and  
Decoder  
A0–A14  
Address  
Inputs  
I/O Buffers  
and Latches  
Y Buffers  
Latches and  
DECODER  
I/O0–I/O7  
Data Inputs/Outputs  
CE  
Control  
OE  
Logic and  
Timing  
WE  
VCC  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  

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