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WS512K32-15G2TIA PDF预览

WS512K32-15G2TIA

更新时间： 2023-08-15 00:00:00
品牌 Logo 应用领域
WEDC 静态存储器
页数 文件大小 规格书
11页 588K
描述
SRAM Module, 512KX32, 15ns, CMOS, CQMA68, CERAMIC, QFP-68

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WS512K32-15G2TIA 数据手册

 浏览型号WS512K32-15G2TIA的Datasheet PDF文件第1页浏览型号WS512K32-15G2TIA的Datasheet PDF文件第2页浏览型号WS512K32-15G2TIA的Datasheet PDF文件第3页浏览型号WS512K32-15G2TIA的Datasheet PDF文件第5页浏览型号WS512K32-15G2TIA的Datasheet PDF文件第6页浏览型号WS512K32-15G2TIA的Datasheet PDF文件第7页 
Read Cycle Time  
tRC  
tAA  
15  
0
17  
0
20  
0
25  
0
35  
0
45  
0
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AddressAccessTime  
15  
17  
20  
25  
35  
45  
55  
OutputHoldfromAddressChange  
Chip Select Access Time  
tOH  
tACS  
tOE  
15  
8
17  
9
20  
10  
25  
12  
35  
25  
45  
25  
55  
25  
OutputEnabletoOutputValid  
ChipSelecttoOutputinLowZ  
OutputEnabletoOutputinLowZ  
ChipDisabletoOutputinHighZ  
OutputDisabletoOutputinHighZ  
tCLZ1  
tOLZ1  
tCHZ1  
tOHZ1  
2
0
2
0
2
0
2
0
4
0
4
0
4
0
12  
12  
12  
12  
12  
12  
12  
12  
15  
15  
20  
20  
20  
20  
*15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.  
1. This parameter is guaranteed by design but not tested.  
Write Cycle Time  
tWC  
tCW  
tAW  
tDW  
tWP  
15  
13  
13  
10  
13  
2
17  
15  
15  
11  
15  
2
20  
15  
15  
12  
15  
2
25  
17  
17  
13  
17  
2
35  
25  
25  
20  
25  
2
45  
35  
35  
25  
35  
2
55  
50  
50  
25  
40  
2
ns  
ChipSelecttoEndofWrite  
AddressValidtoEndofWrite  
DataValidtoEndofWrite  
WritePulseWidth  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AddressSetupTime  
tAS  
AddressHoldTime  
tAH  
0
0
0
0
0
5
5
OutputActivefromEndofWrite  
Write Enable to Output in High Z  
Data Hold Time  
tOW1  
tWHZ1  
tDH  
2
2
3
4
4
5
5
8
9
11  
13  
15  
20  
20  
0
0
0
0
0
0
0
*15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.  
1. This parameter is guaranteed by design but not tested.  
2. The Address Setup Time of minimum 2ns is for the G2T, G1U and H1 packages. tAS minimum for the G4T package is 0ns.  
Input Pulse Levels  
VIL = 0, VIH = 3.0  
V
ns  
V
Input Rise and Fall  
5
InputandOutputReferenceLevel  
Output Timing Reference Level  
1.5  
1.5  
V
Notes:  
VZ is programmable from -2V to +7V.  
IOL & IOH programmable from 0 to 16mA.  
Tester Impedance Z0 = 75 ý.  
VZ is typically the midpoint of VOH and VOL.  
IOL & IOHare adjusted to simulate a typical resistive load circuit.  
ATE tester includes jig capacitance.  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
1234567...11

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