WEDPN4M72V-XB2X
White Electronic Designs
4Mx72 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
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High Frequency = 100, 125, 133MHz
Package:
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
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Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
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Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 4M x 72
Weight: WEDPN4M72V-XB2X - 2 grams typical
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The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option.AnAUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
BENEFITS
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60% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
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Lower inductance and capacitance for low noise
performance
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Suitable for hi-reliability applications
Upgradeable to 8M x 72 density with same footprint
WEDPN8M72V-XB2X
* This product is subject to change without notice..
Discrete Approach
S
A
V
I
ACTUAL SIZE
11.9
54
11.9
11.9
11.9
11.9
21
54
TSOP
White Electronic Designs
WEDPN4M72V-XB2X
54
54
TSOP
54
TSOP
22.3
N
G
S
TSOP
TSOP
21
2
2
2
Area
5 x 265mm = 1328mm
441mm
67%
19%
I/O
5 x 54 pins = 270 pins
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
219 Balls
Count
January 2005
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com