WEDPN4M72V-XB2X
4Mx72 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
High Frequency = 100, 125, 133MHz
The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 67,108,864 bits.
Each chip is internally configured as a quad-bank DRAM with a
synchronous interface. Each of the chip’s 16,777,216-bit banks is
organized as 4,096 rows by 256 columns by 16 bits.
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive edge
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of anACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-11 select
the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location
for the burst access.
of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 4M x 72
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option.AnAUTO PRECHARGE function may be enabled
to provide a self-timed row precharge that is initiated at the end
of the burst sequence.
Weight: WEDPN4M72V-XB2X - 2 grams typical
BENEFITS
60% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
The 256Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible with
the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing
one of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
The 256Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
Upgradeable to 8M x 72 density with same footprint
WEDPN8M72V-XB2X
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with
automatic column-address generation, the ability to interleave
between internal banks in order to hide precharge time and the
capability to randomly change column addresses on each clock
* This product is subject to change without notice.
cycle during a burst access.
Continued on page 4
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
WEDPN4M72V-XB2X
S
A
11.9
11.9
11.9
11.9
11.9
V
I
21
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
22.3
N
G
S
WEDPN4M72V-XB2X
21
Area
5 x 265mm2 = 1,328mm2
5 x 54 balls = 270 pins
441mm2
67%
19%
I/O Count
219 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 3
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
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