Datasheet > WEDPN8M64V-XBX

WEDPN8M64V-XBX

更新时间： 2024-10-01 23:42:03

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
12页	195K
描述
SDRAM MCP

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中文翻译

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WEDPN8M64V-XBX 数据手册

WEDPN8M64V-XBX

8Mx64 Synchronous DRAM

GENERAL DESCRIPTION

FEATURES

The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-

namic random-access memory using 4 chips containing

134,217,728 bits. Each chip is internally configured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 33,554,432-bit banks is organized as 4,096 rows

by 512 columns by 16 bits.

■ High Frequency = 100, 125, 133**MHz

■ Package:

• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm

■ Single 3.3V ± 0.3V power supply

■ Unbuffered

■ Fully synchronous; all signals registered on positive

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an AC-

TIVE command, which is then followed by a READ or WRITE

command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to

be accessed (BA0, BA1 select the bank; A0-11 select the

row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column

location for the burst access.

edge of system clock cycle

■ Internal pipelined operation; column address can be

changed every clock cycle

■ Internal banks for hiding row access/precharge

■ Programmable Burst length 1,2,4,8 or full page

■ 4,096 refresh cycles

■ Commercial, Industrial and Military Temperature Ranges

■ Organized as 8M x 64

• User Configurable as 2 x 8M x 32 or 4 x 8M x 16

■ Weight: WEDPN8M64V-XBX - 2.5 grams typical

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page,

with a burst terminate option. An AUTO PRECHARGE func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst sequence.

BENEFITS

■ 41% SPACE SAVINGS

■ Reduced part count

The 512Mb SDRAM uses an internal pipelined architec-

ture to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on ev-

ery clock cycle to achieve a high-speed, fully random ac-

cess. Precharging one bank while accessing one of the

other three banks will hide the precharge cycles and pro-

vide seamless, high-speed, random-access operation.

■ Low Profile: 2.20 mm (0.087) Max

■ Reduced trace lengths for lower parasitic capacitance

■ Laminate interposer for optimum TCE match

■ Suitable for hi-reliability applications

■ Upgradeable to 16M x 64 density (WEDPN16M64V-XBX)

This product is subject to change without notice.

** 133MHz available at commercial (0^oC to + 70^oC) temperature only.

Discrete Approach

ACTUAL SIZE

11.9

22.3

Area

4 x 265mm²= 1061mm²

625mm²

41%

November 2003 Rev. 13

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7...12

中文翻译

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与WEDPN8M64V-XBX相关器件

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WEDPN8M72V-100B2M	WEDC	获取价格	8Mx72 Synchronous DRAM
WEDPN8M72V-100BC	MICROSEMI	获取价格	Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-270
WEDPN8M72V-100BI	ETC	获取价格	x72 SDRAM Module
WEDPN8M72V-100BM	ETC	获取价格	x72 SDRAM Module
WEDPN8M72V-125B2C	WEDC	获取价格	8Mx72 Synchronous DRAM
WEDPN8M72V-125B2I	WEDC	获取价格	8Mx72 Synchronous DRAM
WEDPN8M72V-125B2M	WEDC	获取价格	8Mx72 Synchronous DRAM
WEDPN8M72V-125BC	ETC	获取价格	x72 SDRAM Module

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