Datasheet > WEDPN8M72VR-XBX

WEDPN8M72VR-XBX

更新时间： 2024-10-01 23:42:03

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
12页	424K
描述
Registered SDRAM MCP

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WEDPN8M72VR-XBX 数据手册

WEDPN8M72VR-XBX

8Mx72 Registered Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ

Registered for enhanced performance of bus speeds of

66 MHz and 100 MHz

Package:

The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-

namic random-access ,memory using 5 chips containing

134,217,728 bits. Each chip is internally configured as a

quad-bank DRAM with a synchronous interface. Each of the

chip’s 33,554,432-bit banks is organized as 4,096 rows by

512 columns by 16 bits. The MCP also incorporates two

16-bit universal bus drivers for address and input control

signals.

ꢀ

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

Single 3.3V ± 0.3V power supply

Fully Synchronous; all signals registered on positive edge

of system clock cycle

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

4096 refresh cycles

Commercial, Industrial and Military Temperature Ranges

Organized as 8M x 72

ꢀ

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE com-

mand, which is then followed by a READ or WRITE com-

mand. The address bits registered coincident with the AC-

TIVE command are used to select the bank and row to be

accessed (BA0, BA1 select the bank; A0-11 select the row).

The address bits registered coincident with the READ or

WRITE command are used to select the starting column lo-

cation for the burst access.

ꢀ

We ight: WEDPN8M72VR-XBX - 2.5 grams typ ic al

BENEFITS

ꢀ

48% SPACE SAVINGS

Reduced part count

Reduced I/O count

• 40% I/O Reduction

Laminate interposer for optimum TCE match

Glueless connection to memory controller/PCI bridge

Suitable for hi-reliability applications

Upgradeable to 16M x 72 density (contact factory for

information)

The SDRAM provides for programmable READ or WRITE burst

lengths of 1, 2, 4 or 8 locations, or the full page, with a

burst terminate option. An AUTO PRECHARGE function may

be enabled to provide a self-timed row precharge that is

initiated at the end of the burst sequence.

ꢀ

The 512Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is com-

patible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock

cycle to achieve a high-sp eed , fully rand om access.

Precharging one bank while accessing one of the other three

banks will hide the precharge cycles and provide seam-

less, high-speed, random-access operation.

* This datasheet describes a product that is subject to change without notice.

The 512Mb SDRAM is designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is provided,

along with a power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance, in-

cluding the ability to synchronously burst data at a high data

rate with automatic column-address generation, the ability

to interleave between internal banks in order to hide

precharge time and the capability to randomly change col-

umn addresses on each clock cycle during a burst access.

November 2003 Rev. 4

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7...12

中文翻译

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与WEDPN8M72VR-XBX相关器件

型号	品牌	获取价格	描述	数据表
WEDPN8M72V-XB2X	WEDC	获取价格	8Mx72 Synchronous DRAM
WEDPN8M72V-XBX	ETC	获取价格	SDRAM MCP
WEDPND16M72S-200BC	WEDC	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-200BI	WEDC	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-200BM	WEDC	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-250BC	WEDC	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-250BI	WEDC	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-250BM	MICROSEMI	获取价格	DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-266BC	WEDC	获取价格	DDR DRAM, 16MX72, 0.75ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPND16M72S-266BI	WEDC	获取价格	DDR DRAM, 16MX72, 0.75ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

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