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WEDPN8M64V-100B2M

更新时间： 2024-10-02 03:05:19

品牌	Logo	应用领域
WEDC		存储动态存储器
页数	文件大小	规格书
15页	460K
描述
8Mx64 Synchronous DRAM

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WEDPN8M64V-XB2X

White Electronic Designs

8Mx64 Synchronous DRAM

GENERAL DESCRIPTION

FEATURES

The 64MByte (512Mb) SDRAM is a high-speed CMOS,

dynamic random-access memory using 4 chips containing

134,217,728 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 33,554,432-bit banks is organized as 4,096 rows

by 512 columns by 16 bits.

ꢀ

High Frequency = 100, 125, 133MHz

Package:

•

219 Plastic Ball Grid Array (PBGA), 21 x 21mm

ꢀ

Single 3.3V 0.3V ꢀpoer ꢁuꢀꢀly

Unbuffered

Fully ꢁynchrpnpuꢁ; all ꢁignalꢁ regiꢁtered pn ꢀpꢁitive edge pf

ꢁyꢁtem clpck cycle

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

11 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

ꢀ

Internal ꢀiꢀelined pꢀeratipn; cplumn addreꢁꢁ can be changed

every clpck cycle

ꢀ

Internal bankꢁ fpr hiding rpo acceꢁꢁ/ꢀrecharge

Prpgrammable Burꢁt length 1,2,4,8 pr full ꢀage

4,096 refreꢁh cycleꢁ

Cpmmercial, Induꢁtrial and Military Temꢀerature Rangeꢁ

Organized aꢁ 8M x 64

•

User Conﬁgurable as 2 x 8M x 32 or

4 x 8M x 16

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

ꢀ

Weight: WEDPN8M64V-XB2X - 2 gramꢁ tyꢀical

BENEFITS

ꢀ

58% SPACE SAVINGS

Reduced ꢀart cpunt

Reduced trace lengthꢁ fpr lpoer ꢀaraꢁitic caꢀacitance

Laminate interꢀpꢁer fpr pꢀtimum TCE match

Suitable fpr hi-reliability aꢀꢀlicatipnꢁ

The 512Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

Uꢀgradeable tp 16M x 64 denꢁity (WEDPN16M64V-XB2X)

* Thiꢁ ꢀrpduct iꢁ ꢁubject tp change oithput nptice.

Discrete Approach

ACTUAL SIZE

11.9

22.3

WEDPN8M64V-XB2X

Area

4 x 265mm = 1060mm

441mm

58%

January 2005

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

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与WEDPN8M64V-100B2M相关器件

型号	品牌	获取价格	描述	数据表
WEDPN8M64V-100BC	WEDC	获取价格	Synchronous DRAM Module, 8MX64, 7ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219
WEDPN8M64V-100BM	WEDC	获取价格	Synchronous DRAM Module, 8MX64, 7ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219
WEDPN8M64V-125B2C	WEDC	获取价格	8Mx64 Synchronous DRAM
WEDPN8M64V-125B2I	WEDC	获取价格	8Mx64 Synchronous DRAM
WEDPN8M64V-125B2M	WEDC	获取价格	8Mx64 Synchronous DRAM
WEDPN8M64V-125BC	WEDC	获取价格	Synchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219
WEDPN8M64V-125BI	WEDC	获取价格	Synchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219
WEDPN8M64V-133B2C	WEDC	获取价格	8Mx64 Synchronous DRAM
WEDPN8M64V-133B2I	WEDC	获取价格	8Mx64 Synchronous DRAM
WEDPN8M64V-133B2M	WEDC	获取价格	8Mx64 Synchronous DRAM

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