Datasheet > WEDPN4M72V-125BC

WEDPN4M72V-125BC

更新时间： 2024-10-03 08:42:27

品牌	Logo	应用领域
WEDC		动态存储器内存集成电路
页数	文件大小	规格书
14页	463K
描述
Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219

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WEDPN4M72V-125BC 数据手册

WEDPN4M72V-XBX

White Electronic Designs

4Mx72 Synchronous DRAM*

FEATURES

GENERAL DESCRIPTION



High Frequency = 100, 125MHz

The 32MByte (256Mb) SDRAM is a high-speed CMOS,

dynamic random-access ,memory using 5 chips containing

67,108,864 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 16,777,216-bit banks is organized as 4,096 rows

by 256 columns by 16 bits.



Package:



219 Plastic Ball Grid Array (PBGA), 25 x 21mm



Single 3.3V ±0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

11 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.



Internal pipelined operation; column address can be

changed every clock cycle



Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

4096 refresh cycles

Commercial, Industrial and Military Temperature

Ranges



Organized as 4M x 72

Weight: WEDPN4M72V-XBX - 2 grams typical

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

BENEFITS



60% SPACE SAVINGS

Reduced part count

Reduced I/O count

The 256Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.



19% I/O Reduction



Lower inductance and capacitance for low noise

performance



Suitable for hi-reliability applications

Upgradeable to 8M x 72 density with same footprint

(contact factory for information)

* This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X

for new designs.

Discrete Approach

11.9

ACTUAL SIZE

11.9

TSOP

White Electronic Designs

WEDPN4M72V-XBX

TSOP

22.3

Area

5 x 265mm²= 1328mm²

5 x 54 pins = 270 pins

525mm²

219 Balls

60%

19%

I/O

Count

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

April, 2004

Rev. 15

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...14

中文翻译

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与WEDPN4M72V-125BC相关器件

型号	品牌	获取价格	描述	数据表
WEDPN4M72V-125BI	WEDC	获取价格	Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-133B2C	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-133B2C	MICROSEMI	获取价格	Synchronous DRAM, 4MX72, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-133B2I	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-133B2I	MICROSEMI	获取价格	Synchronous DRAM, 4MX72, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-133B2M	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-133B2M	MICROSEMI	获取价格	暂无描述
WEDPN4M72V-XB2X	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-XBX	ETC	获取价格	SDRAM MCP
WEDPN8M64V-100B2C	WEDC	获取价格	8Mx64 Synchronous DRAM

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