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WEDPN4M72V-100B2I PDF预览

WEDPN4M72V-100B2I

更新时间： 2024-09-30 20:20:59
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟动态存储器内存集成电路
页数 文件大小 规格书
13页 913K
描述
Synchronous DRAM, 4MX72, 7ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219

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WEDPN4M72V-100B2I 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA219,16X16,50针数：219
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.28风险等级：5.75
Is Samacsys：N访问模式：FOUR BANK PAGE BURST
最长访问时间：7 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：S-PBGA-B219内存密度：301989888 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：72
功能数量：1端口数量：1
端子数量：219字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX72输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA219,16X16,50封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
刷新周期：4096自我刷新：YES
子类别：DRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

WEDPN4M72V-100B2I 数据手册

 浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第2页浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第3页浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第4页浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第5页浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第6页浏览型号WEDPN4M72V-100B2I的Datasheet PDF文件第7页 
WEDPN4M72V-XB2X  
4Mx72 Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
 High Frequency = 100, 125, 133MHz  
The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic  
random-access ,memory using 5 chips containing 67,108,864 bits.  
Each chip is internally configured as a quad-bank DRAM with a  
synchronous interface. Each of the chip’s 16,777,216-bit banks is  
organized as 4,096 rows by 256 columns by 16 bits.  
 Package:  
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm  
 Single 3.3V ±0.3V power supply  
 Fully Synchronous; all signals registered on positive edge  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a programmed  
number of locations in a programmed sequence. Accesses begin  
with the registration of anACTIVE command, which is then followed  
by a READ or WRITE command. The address bits registered  
coincident with the ACTIVE command are used to select the bank  
and row to be accessed (BA0, BA1 select the bank; A0-11 select  
the row). The address bits registered coincident with the READ or  
WRITE command are used to select the starting column location  
for the burst access.  
of system clock cycle  
 Internal pipelined operation; column address can be  
changed every clock cycle  
 Internal banks for hiding row access/precharge  
 Programmable Burst length 1,2,4,8 or full page  
 4096 refresh cycles  
 Commercial, Industrial and Military Temperature Ranges  
 Organized as 4M x 72  
The SDRAM provides for programmable READ or WRITE burst  
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst  
terminate option.AnAUTO PRECHARGE function may be enabled  
to provide a self-timed row precharge that is initiated at the end  
of the burst sequence.  
 Weight: WEDPN4M72V-XB2X - 2 grams typical  
BENEFITS  
 60% SPACE SAVINGS  
 Reduced part count  
 Reduced I/O count  
• 19% I/O Reduction  
The 256Mb SDRAM uses an internal pipelined architecture to  
achieve high-speed operation. This architecture is compatible with  
the 2n rule of prefetch architectures, but it also allows the column  
address to be changed on every clock cycle to achieve a high-  
speed, fully random access. Precharging one bank while accessing  
one of the other three banks will hide the precharge cycles and  
provide seamless, high-speed, random-access operation.  
 Lower inductance and capacitance for low noise  
performance  
 Suitable for hi-reliability applications  
The 256Mb SDRAM is designed to operate in 3.3V, low-power  
memory systems. An auto refresh mode is provided, along with a  
power-saving, power-down mode.  
 Upgradeable to 8M x 72 density with same footprint  
WEDPN8M72V-XB2X  
All inputs and outputs are LVTTL compatible. SDRAMs offer  
substantial advances in DRAM operating performance, including  
the ability to synchronously burst data at a high data rate with  
automatic column-address generation, the ability to interleave  
between internal banks in order to hide precharge time and the  
capability to randomly change column addresses on each clock  
* This product is subject to change without notice.  
cycle during a burst access.  
Continued on page 4  
FIGURE 1 – DENSITY COMPARISONS  
CSP Approach (mm)  
WEDPN4M72V-XB2X  
S
A
11.9  
11.9  
11.9  
11.9  
11.9  
V
I
21  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
22.3  
N
G
S
WEDPN4M72V-XB2X  
21  
Area  
5 x 265mm2 = 1,328mm2  
5 x 54 balls = 270 pins  
441mm2  
67%  
19%  
I/O Count  
219 Balls  
Microsemi Corporation reserves the right to change products or specifications without notice.  
February 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 3  
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com  
www.microsemi.com  
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WEDPN4M72V-125B2I WEDC

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 		4Mx72 Synchronous DRAM
WEDPN4M72V-125B2I MICROSEMI

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 		4Mx72 Synchronous DRAM
WEDPN4M72V-125B2M MICROSEMI

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WEDPN4M72V-125BC WEDC

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 		Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
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 		Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
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 		4Mx72 Synchronous DRAM
WEDPN4M72V-133B2C MICROSEMI

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 		Synchronous DRAM, 4MX72, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219

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