Datasheet > WEDPN4M72V-100B2M

WEDPN4M72V-100B2M

更新时间： 2024-02-20 08:33:51

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
15页	331K
描述
4Mx72 Synchronous DRAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

WEDPN4M72V-100B2M 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	BGA,	Reach Compliance Code：	unknown
风险等级：	5.75	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	7 ns	其他特性：	AUTO/SELF REFRESH
JESD-30 代码：	S-PBGA-B219	内存密度：	301989888 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	72
功能数量：	1	端口数量：	1
端子数量：	219	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	4MX72	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.64 mm
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

WEDPN4M72V-100B2M 数据手册

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第2页

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第3页

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第4页

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第5页

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第6页

浏览型号WEDPN4M72V-100B2M的Datasheet PDF文件第7页

WEDPN4M72V-XB2X

White Electronic Designs

4Mx72 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ

High Frequency = 100, 125, 133MHz

Package:

The 32MByte (256Mb) SDRAM is a high-speed CMOS,

dynamic random-access ,memory using 5 chips containing

67,108,864 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 16,777,216-bit banks is organized as 4,096 rows

by 256 columns by 16 bits.

• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm

Single 3.3V 0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

ꢀ

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

11 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

ꢀ

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

4096 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

Organized as 4M x 72

Weight: WEDPN4M72V-XB2X - 2 grams typical

ꢀ

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

BENEFITS

ꢀ

60% SPACE SAVINGS

Reduced part count

Reduced I/O count

• 19% I/O Reduction

The 256Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

ꢀ

Lower inductance and capacitance for low noise

performance

ꢀ

Suitable for hi-reliability applications

Upgradeable to 8M x 72 density with same footprint

WEDPN8M72V-XB2X

* This product is subject to change without notice..

Discrete Approach

ACTUAL SIZE

11.9

TSOP

White Electronic Designs

WEDPN4M72V-XB2X

TSOP

22.3

TSOP

Area

5 x 265mm = 1328mm

441mm

67%

19%

I/O

5 x 54 pins = 270 pins

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

219 Balls

Count

January 2005

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

中文翻译

下载PDF

与WEDPN4M72V-100B2M相关器件

型号	品牌	获取价格	描述	数据表
WEDPN4M72V-125B2C	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-125B2I	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-125B2I	MICROSEMI	获取价格	Synchronous DRAM, 4MX72, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-125B2M	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-125B2M	MICROSEMI	获取价格	Synchronous DRAM, 4MX72, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-125BC	WEDC	获取价格	Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-125BI	WEDC	获取价格	Synchronous DRAM Module, 4MX72, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-133B2C	WEDC	获取价格	4Mx72 Synchronous DRAM
WEDPN4M72V-133B2C	MICROSEMI	获取价格	Synchronous DRAM, 4MX72, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN4M72V-133B2I	WEDC	获取价格	4Mx72 Synchronous DRAM

与WEDPN4M72V-100B2M相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

16
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

15
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

13
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

16

产品中心

服务支持

精选活动

关于我们

帮助中心

WEDPN4M72V-100B2M

WEDPN4M72V-100B2M 技术参数

WEDPN4M72V-100B2M 数据手册

与WEDPN4M72V-100B2M相关器件

与WEDPN4M72V-100B2M相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

WEDPN4M72V-100B2M

WEDPN4M72V-100B2M 技术参数

WEDPN4M72V-100B2M 数据手册

与WEDPN4M72V-100B2M相关器件

与WEDPN4M72V-100B2M相关文章

您还可以找

您在本页遇到什么问题？