WEDPN4M64V-XBX
White Electronic Designs
4Mx64 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
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High Frequency = 100, 125, 133MHz
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 4 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
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Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V 0.3V power supply
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Fully Synchronous; all signals registered on positive
edge of system clock cycle
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence.Accesses begin with the registration of anACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0, BA1 select the bank; A0-11 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
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Internal pipelined operation; column address can be
changed every clock cycle
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Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
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Organized as 4M x 64
• User Configurable as 2x4Mx32 or 4x4Mx16
Weight: WEDPN4M64V-XBX - 2 grams typical
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
BENEFITS
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58% SPACE SAVINGS
The 256Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
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Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 8M x 64 (contact factory for
availability)
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
*This product is subject to change without notice.
Discrete Approach
S
A
V
I
ACTUAL SIZE
11.9
21
54
TSOP
54
TSOP
54
TSOP
54
TSOP
WEDPN4M64V-XBX
22.3
N
G
S
21
2
2
2
Area
4 x 265mm = 1061mm
441mm
58%
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com