WEDPN16M72VR-XB2X
White Electronic Designs
16MX72 REGISTERED SYNCHRONOUS DRAM
FEATURES
GENERAL DESCRIPTION
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Registered for enhanced performance of bus
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.
speeds
• 100, 125, 133**MHz
Package:
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• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
Single 3.3V 0.3V power supply
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Fully Synchronous; all signals registered on positive
edge of system clock cycle
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
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Internal pipelined operation; column address can be
changed every clock cycle
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Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
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Organized as 16M x 72
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option.AnAUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
Weight: WEDPN16M72VR-XB2X - 2.5 grams
typical
BENEFITS
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59% SPACE SAVINGS
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
Reduced part count
Reduced I/O count
• 40% I/O Reduction
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Reduced trace lengths for lower parasitic
capacitance
Glueless connection to memory controller/PCI
bridge
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems.An auto refresh mode is provided, along
with a power-saving, power-down mode.
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Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
All inputs and outputs are LVTTLcompatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
* This product is subject to change without notice.
** Available at commercial and industrial temperatures only.
January 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com