Datasheet > WEDPN16M72V-XB2X

WEDPN16M72V-XB2X

更新时间： 2024-09-30 03:18:31

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
14页	442K
描述
16Mx72 Synchronous DRAM

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WEDPN16M72V-XB2X 数据手册

WEDPN16M72V-XB2X

White Electronic Designs

16Mx72 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ

High Frequency = 100, 125, 133MHz

Package:

The 128MByte (1Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 5 chips containing

268,435,456 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 67,108,864-bit banks is organized as 8,192 rows

by 512 columns by 16 bits.

• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm

Single 3.3V 0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

ꢀ

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

Organized as 16M x 72

Weight: WEDPN16M72V-XB2X - 2.5 grams typical

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-12

select the row). The address bits registered coincident

with the READ or WRITE command are used to select

the starting column location for the burst access.

ꢀ

BENEFITS

ꢀ

60% SPACE SAVINGS

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

Reduced part count

Reduced I/O count

• 19% I/O Reduction

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

Upgradeable to 32M x 72 density (contact factory

for information)

ꢀ

The 1Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is compatible

with the 2n rule of prefetch architectures, but it also allows

the column address to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide

the precharge cycles and provide seamless, high-speed,

random-access operation.

ꢀ

* This product is subject to change without notice.

Discrete Approach

ACTUAL SIZE

11.9

TSOP

White Electronic Designs

22.3

TSOP

WEDPN16M72V-XB2X

Area

5 x 265mm²= 1328mm²

5 x 54 pins = 270 pins

525mm²

219 Balls

60%

19%

I/O

Count

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

February 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...14

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