Datasheet > WEDPN16M72VR-125B3I

WEDPN16M72VR-125B3I

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
美高森美 - MICROSEMI		动态存储器
页数	文件大小	规格书
13页	608K
描述
Synchronous DRAM, 16MX72, 5.8ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

WEDPN16M72VR-125B3I 数据手册

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第2页

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第3页

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第4页

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第5页

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第6页

浏览型号WEDPN16M72VR-125B3I的Datasheet PDF文件第7页

WEDPN16M72VR-XB3X

16MX72 REGISTERED SYNCHRONOUS DRAM

FEATURES

GENERAL DESCRIPTION

 Registered for enhanced performance of bus speeds

The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic

random-access, memory using 5 chips containing 268,435,456

bits. Each chip is internally conﬁgured as a quad-bank DRAM with

a synchronous interface. Each of the chip’s 67,108,864-bit banks

is organized as 8,192 rows by 512 columns by 16 bits. The MCP

also incorporates two 16-bit universal bus drivers for input control

signals and addresses.

• 100, 125, 133MHz

 Package:

• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm

 Single 3.3V ±0.3V power supply

 Fully Synchronous; all signals registered on positive edge

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin

with the registration of anACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-12 select

the row). The address bits registered coincident with the READ or

WRITE command are used to select the starting column location

for the burst access.

of system clock cycle

 Internal pipelined operation; column address can be

changed every clock cycle

 Internal banks for hiding row access/precharge

 Programmable Burst length 1,2,4,8 or full page

 8,192 refresh cycles

 Commercial, Industrial and Military Temperature Ranges

 Organized as 16M x 72

The SDRAM provides for programmable READ or WRITE burst

lengths of 1, 2, 4 or 8 locations, or the full page, with a burst

terminate option.AnAUTO PRECHARGE function may be enabled

to provide a self-timed row precharge that is initiated at the end

of the burst sequence.

 Weight: WEDPN16M72VR-XB3X - 2.5 grams typical

BENEFITS

 59% SPACE SAVINGS

 Reduced part count

The 1Gb SDRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compatible with the 2n

rule of prefetch architectures, but it also allows the column address

to be changed on every clock cycle to achieve a high-speed, fully

random access. Precharging one bank while accessing one of

the other three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

 Reduced I/O count

• 40% I/O Reduction

 Reduced trace lengths for lower parasitic capacitance

 Glueless connection to memory controller/PCI bridge

 Suitable for hi-reliability applications

 Laminate interposer for optimum TCE match

The 1Gb SDRAM is designed to operate in 3.3V, low-power

memory systems. An auto refresh mode is provided, along with a

power-saving, power-down mode.

* This product is subject to change without notice.

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance, including

the ability to synchronously burst data at a high data rate with

automatic column-address generation, the ability to interleave

between internal banks in order to hide precharge time and the

capability to randomly change column addresses on each clock

cycle during a burst access.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 1

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

12 3 4 5 6 7...13

中文翻译

下载PDF

与WEDPN16M72VR-125B3I相关器件

型号	品牌	获取价格	描述	数据表
WEDPN16M72VR-125B3M	MICROSEMI	获取价格	Synchronous DRAM, 16MX72, 5.8ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M72VR-125BC	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX72, 5.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M72VR-125BM	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX72, 5.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M72VR-133B2C	WEDC	获取价格	16MX72 REGISTERED SYNCHRONOUS DRAM
WEDPN16M72VR-133B2I	WEDC	获取价格	16MX72 REGISTERED SYNCHRONOUS DRAM
WEDPN16M72VR-133B2M	WEDC	获取价格	16MX72 REGISTERED SYNCHRONOUS DRAM
WEDPN16M72VR-133B3C	MICROSEMI	获取价格	Synchronous DRAM, 16MX72, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M72VR-133BC	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M72VR-66BC	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX72, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M72VR-66BI	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX72, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

与WEDPN16M72VR-125B3I相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

4
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

3
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

3
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

5

产品中心

服务支持

精选活动

关于我们

帮助中心

WEDPN16M72VR-125B3I

WEDPN16M72VR-125B3I 数据手册

与WEDPN16M72VR-125B3I相关器件

与WEDPN16M72VR-125B3I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

WEDPN16M72VR-125B3I

WEDPN16M72VR-125B3I 数据手册

与WEDPN16M72VR-125B3I相关器件

与WEDPN16M72VR-125B3I相关文章

您还可以找

您在本页遇到什么问题？