Datasheet > WCMA2008U1B-FF70

WCMA2008U1B-FF70

更新时间： 2022-11-25 19:04:43

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
11页	144K
描述
256K x 8 Static RAM

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数据手册

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WCMA2008U1B-FF70 数据手册

WCMA2008U1B

Switching Characteristics Over the Operating Range^[5]

WCMA2008U1B-70

Parameter

READ CYCLE

Description

Min.

Max.

Unit

t_RC

Read Cycle Time

t_AA

Address to Data Valid

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

Data Hold from Address Change

CE₁LOW and CE₂HIGH to Data Valid

OE LOW to Data Valid

[6]

OE LOW to Low Z

OE HIGH to High Z^{[6, 7]}

[6]

CE₁LOW and CE₂HIGH to Low Z

CE₁HIGH or CE₂LOW to High Z^{[6, 7]}

CE₁LOW and CE₂HIGH to Power-Up

CE₁HIGH or CE₂LOW to Power-Down

t_PD

[8,]

WRITE CYCLE

t_WC

t_SCE

t_AW

Write Cycle Time

CE₁LOW and CE₂HIGH to Write End

Address Set-Up to Write End

Address Hold from Write End

Address Set-Up to Write Start

WE Pulse Width

t_HA

t_SA

t_PWE

t_SD

Data Set-Up to Write End

Data Hold from Write End

WE LOW to High Z^{[6, 7]}

WE HIGH to Low Z^[6]

t_HD

t_HZWE

t_LZWE

Notes:

5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V_CC(typ.)/2, input pulse levels of 0 to V_CC(typ.), and output loading

of the specified I_OL/I_OHand 30 pF load capacitance.

6. At any given temperature and voltage condition, t_HZCEis less than t_LZCE, t_HZOEis less than t_LZOE, and t_HZWEis less than t_LZWEfor any given device.

7. t_HZOE, t_HZCE, and t_HZWEtransitions are measured when the outputs enter a high impedance state.

8. The internal write time of the memory is defined by the overlap of WE, CE₁= V_IL, and CE = V_IH. All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that

terminates the write.

1 2 3 456 7 8...11

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