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W946432AD-6 PDF预览

W946432AD-6

更新时间: 2024-01-13 07:14:39
品牌 Logo 应用领域
华邦 - WINBOND 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
40页 451K
描述
DDR DRAM, 2MX32, 0.1ns, CMOS, PQFP100

W946432AD-6 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:LQFP, QFP100,.63X.87
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.88
访问模式:FOUR BANK PAGE BURST最长访问时间:0.1 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):166 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:67108864 bit
内存集成电路类型:DDR DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:100字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5 V认证状态:Not Qualified
座面最大高度:1.6 mm自我刷新:YES
连续突发长度:2,4,8子类别:DRAMs
最大供电电压 (Vsup):2.65 V最小供电电压 (Vsup):2.35 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

W946432AD-6 数据手册

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W946432AD  
PIN DESCRIPTION  
PIN NAME  
FUNCTION  
DESCRIPTION  
All address and control input signals are sampled on the crossing of the positive edge of CLK  
and negative edge of . Output (read) data is referenced to the crossings of CLK and  
Differential clock  
input  
CLK  
(both directions of crossing).  
CLK,  
CLK  
CLK  
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input  
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and  
SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any  
bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.  
CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be  
CKE  
Clock Enable  
maintained high throughout READ and WRITE accesses. Input buffers, excluding CLK,  
CLK  
and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled  
during SELF REFRESH.  
All commands are masked when  
is registered HIGH.  
provides for external bank  
CS  
CS  
Chip Select  
CS  
selection on systems with multiple banks.  
is considered part of the command code.  
CS  
,
,
RAS CAS  
Command Inputs  
,
and WE (along with  
) define the command being entered.  
CS  
RAS CAS  
WE  
DM is an input mask signal for writes data. Input data is masked when DM is sampled HIGH  
along with that input data during a WRITE access. DM is sampled on both edges of DQS.  
Although DM pins are input only, the DM loading matches the DQ and DQS loading.  
DM  
Input Data Mask  
Bank Address  
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is  
being applied.  
BA0, BA1  
Provide the row address for ACTIVE commands, and the column address and AUTO  
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array  
in the respective bank. A8 is sampled during a PRECHARGE command to determine whether  
the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is  
to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-  
code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is  
loaded during the MODE REGISTER SET command (MRS or EMRS).  
A0-A10  
Address Input  
DQ  
Data Input/Output Data bus  
Output with read data, input with write data. Edge-aligned with read data, centered in write  
data. Used to capture write data.  
DQS  
Data Strobe  
VDDQ  
VSSQ  
DQ Power  
2.5V ± 0.2V.  
Ground.  
DQ Ground  
Supply Power  
VDD  
VSS  
NC  
2.5V ± 0.2V  
Ground.  
No Connection  
No connection  
VREF  
SSTL_2 reference voltage.  

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