Datasheet > W40S11-23H

W40S11-23H

更新时间： 2024-11-15 23:41:35

品牌	Logo	应用领域
其他 - ETC		时钟驱动器逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
11页	187K
描述
THIRTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|CMOS\|SSOP\|28PIN\|PLASTIC

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中文翻译

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数据手册

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W40S11-23H 数据手册

1W40S11-23

W40S11-23

Clock Buffer/Driver

Features

Key Specifications

• Thirteen skew-controlled CMOS clock outputs

(SDRAM0:12)

• Supports three SDRAM DIMMs

• Ideal for high-performance systems designed around

Intel’s latest chip set

• SMBus serial configuration interface

• ClockSkew betweenanytwooutputsislessthan250ps

• 1- to 5-ns propagation delay

• DC to 133-MHz operation

• Single 3.3V supply voltage

• Low power CMOS design packaged in a 28-pin, 300-mil

SOIC (Small Outline Integrated Circuit), 28-pin, 173-mil

(Thin Shrink Small Outline Package), and 28-pin,

209-mil SSOP (Small Shrink Outline Package)

Supply Voltages:........................................... V_DD= 3.3V±5%

Operating Temperature:.................................... 0°C to +70°C

Input Threshold: ..................................................1.5V typical

Maximum Input Voltage:.......................................V_DD+ 0.5V

Input Frequency:............................................... 0 to 133 MHz

BUF_IN to SDRAM0:12 Propagation Delay: ......1.0 to 5.0 ns

Output Edge Rate:.............................................. >1.5 V/ns

Output Clock Skew:.................................................. ±250 ps

Output Duty Cycle: .................................. 45/55% worst case

Output Impedance:...............................................15Ω typical

Output Type: ................................................CMOS rail-to-rail

Overview

The Cypress W40S11-23 is a low-voltage, thirteen-output

clock buffer. Output buffer impedance is approximately 15Ω,

which is ideal for driving SDRAM DIMMs.

Pin Configuration

Block Diagram

SOIC

SDATA

SCLOCK

Serial Port

Device Control

VDD

SDRAM0

SDRAM1

GND

VDD

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM11

SDRAM10

GND

VDD

SDRAM2

SDRAM3

GND

SDRAM9

SDRAM8

GND

BUF_IN

SDRAM4

SDRAM5

SDRAM12

VDD

SDRAM7

SDRAM6

GND

SCLOCK

SDRAM7

SDRAM8

SDRAM9

SDRAM10

SDRAM11

[1]

SDATA

BUF_IN

Note:

1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs

(not CMOS level).

SDRAM12

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

April 6, 2001

12 3 4 5 6 7...11

中文翻译

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与W40S11-23H相关器件

型号	品牌	获取价格	描述	数据表
W40S11-23X	CYPRESS	获取价格	Low Skew Clock Driver, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.173 INCH,
W40S11-23XT	CYPRESS	获取价格	Low Skew Clock Driver, W40 Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28,
W40S11-23Z	CYPRESS	获取价格	Low Skew Clock Driver, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.209 INCH,
W40S12-24G	CYPRESS	获取价格	Low Skew Clock Driver, S Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PDSO32, 0.
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W4120GG5000	PULSE	获取价格	IP67 Active 6 Band GPS Antenna
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