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W40S11-23Z PDF预览

W40S11-23Z

更新时间: 2024-11-16 21:13:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 206K
描述
Low Skew Clock Driver, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.209 INCH, SSOP-28

W40S11-23Z 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:13最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

W40S11-23Z 数据手册

 浏览型号W40S11-23Z的Datasheet PDF文件第2页浏览型号W40S11-23Z的Datasheet PDF文件第3页浏览型号W40S11-23Z的Datasheet PDF文件第4页浏览型号W40S11-23Z的Datasheet PDF文件第5页浏览型号W40S11-23Z的Datasheet PDF文件第6页浏览型号W40S11-23Z的Datasheet PDF文件第7页 
W40S11-23  
Clock Buffer/Driver  
Features  
Key Specifications  
• Thirteen skew-controlled CMOS clock outputs  
(SDRAM0:12)  
• Supports three SDRAM DIMMs  
• Ideal for high-performance systems designed around  
Intel’s latest chip set  
Supply Voltages:........................................... V = 3.3V±5%  
DD  
Operating Temperature:.................................... 0°C to +70°C  
Input Threshold: .................................................. 1.5V typical  
Maximum Input Voltage:.......................................V + 0.5V  
DD  
• SMBus serial configuration interface  
• Clock Skew between any two outputs is less than 250 ps  
• 1- to 5-ns propagation delay  
• DC to 133-MHz operation  
• Single 3.3V supply voltage  
• Low power CMOS design packaged in a 28-pin, 300-mil  
SOIC (Small Outline Integrated Circuit), 28-pin, 173-mil  
(Thin Shrink Small Outline Package), and 28-pin,  
209-mil SSOP (Small Shrink Outline Package)  
Input Frequency:............................................... 0 to 133 MHz  
BUF_IN to SDRAM0:12 Propagation Delay: ......1.0 to 5.0 ns  
Output Edge Rate:.............................................. >1.5 V/ns  
Output Clock Skew: .................................................. ±250 ps  
Output Duty Cycle: .................................. 45/55% worst case  
Output Impedance:...............................................15typical  
Output Type: ................................................ CMOS rail-to-rail  
Overview  
The Cypress W40S11-23 is a low-voltage, thirteen-output  
clock buffer. Output buffer impedance is approximately 15,  
which is ideal for driving SDRAM DIMMs.  
Pin Configuration  
Block Diagram  
SOIC  
SDATA  
SCLOCK  
Serial Port  
Device Control  
VDD  
SDRAM0  
SDRAM1  
GND  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
SDRAM0  
SDRAM1  
SDRAM2  
SDRAM3  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM11  
SDRAM10  
GND  
VDD  
VDD  
SDRAM2  
SDRAM3  
GND  
SDRAM9  
SDRAM8  
GND  
BUF_IN  
SDRAM4  
SDRAM5  
SDRAM12  
VDD  
9
VDD  
10  
11  
12  
13  
14  
SDRAM7  
SDRAM6  
GND  
GND  
SCLOCK  
SDRAM7  
SDRAM8  
SDRAM9  
[1]  
[1]  
SDATA  
BUF_IN  
Note:  
SDRAM10  
SDRAM11  
1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs  
(not CMOS level).  
SDRAM12  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 20, 2000, Rev. *A  

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