Datasheet > W3EG64128S-BD4

W3EG64128S-BD4

更新时间： 2024-09-17 04:25:43

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
9页	137K
描述
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL

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W3EG64128S-BD4 数据手册

W3EG64128S-AD4

-BD4

White Electronic Designs

PRELIMINARY*

1GB – 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG64128S is a 2x64Mx64 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

component. The module consists of eight 128Mx8 stack

DDR SDRAMs in 66 pin TSOP packages mounted on a

200 pin FR4 substrate.

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Serial presence detect

Dual Rank

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Power supply: 2.5V 0.2V

JEDEC standard 200 pin SO-DIMM package

•

Package height options:

BD4: 31.75 mm (1.25”)

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

OPERATING FREQUENCIES

DDR333 @CL=2.5

166MHz

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2.5-3-3

2-2-2

2.5-3-3

2-2-2

May 2004

Rev. 0

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...9

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