Datasheet > W3EG64129S-D3

W3EG64129S-D3

更新时间： 2024-11-07 04:25:43

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
8页	124K
描述
1G- 128Mx64 DDR SDRAM UNBUFFERED

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中文翻译

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W3EG64129S-D3 数据手册

W3EG64129S-D3

White Electronic Designs

PRELIMINARY*

1G- 128Mx64 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

ꢀ

Clock speeds of 100MHz and 133MHz

The W3EG64129S is a 124Mx64 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

component. The module consists of sixteen 128Mx4 DDR

SDRAMs in 66 pin TSOP package mounted on a 184 Pin

FR4 substrate.

Double-data-rate architecture

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2,5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lenths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Power Supply: 2.5V 0.20V

JEDEC standard 184 pin DIMM package

OPERATING FREQUENCIES

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2-2-2

2.5-3-3

2-2-2

June 2004

Rev. 0

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7 8

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