Datasheet > W25P243A

W25P243A

更新时间： 2024-11-14 22:14:55

品牌	Logo	应用领域
华邦 - WINBOND		/
页数	文件大小	规格书
18页	265K
描述
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

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W25P243A 数据手册

W25P243A

64K ´ 64 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

GENERAL DESCRIPTION

The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM

organized as 65,536 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst

address counter supports both Pentium burst mode and linear burst mode. The mode to be

LBO

executed is controlled by the

pin. Pipelining or non-pipelining of the data outputs is controlled by

pin. A snooze mode can reduce power dissipation.

the

W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the

device is deselected by CE2/CE3 .

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

Synchronous operation

Pipelined data output capability

High-speed access time: 4.5/5/6 nS (max.)

Single +3.3V power supply

Supports snooze mode (low-power state)

Internal burst counter supports Intel burst

(Interleaved) mode & linear burst mode

Individual byte write capability

3.3V LVTTL compatible I/O

Support 2T/1T mode

Clock-controlled and registered input

Asynchronous output enable

Packaged in 128-pin QFP and TQFP

BLOCK DIAGRAM

INPUT

A(15:0)

64K X 64

CORE

ARRAY

CLK

CE(3:1)

BWE

CONTROL

LOGIC

BW(8:1)

DATA I/O

I/O(64:1)

ADSC

ADSP

ADV

LBO

Publication Release Date: August 1999

Revision A3

- 1 -

12 3 4 5 6 7...18

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