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W25P243AF-5 PDF预览

W25P243AF-5

更新时间: 2024-11-14 22:13:47
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
18页 265K
描述
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

W25P243AF-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP-128
针数:128Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:5 ns
I/O 类型:COMMONJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:64功能数量:1
端子数量:128字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX64输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP128,.67X.93,20封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:3.4 mm
最大待机电流:0.005 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.35 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

W25P243AF-5 数据手册

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W25P243A  
64K ´ 64 BURST PIPELINED HIGH-SPEED  
CMOS STATIC RAM  
GENERAL DESCRIPTION  
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM  
´
organized as 65,536 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst  
ä
address counter supports both Pentium burst mode and linear burst mode. The mode to be  
LBO  
executed is controlled by the  
pin. Pipelining or non-pipelining of the data outputs is controlled by  
pin. A snooze mode can reduce power dissipation.  
FT  
the  
W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the  
device is deselected by CE2/CE3 .  
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.  
FEATURES  
·
·
·
·
·
·
·
·
·
·
Synchronous operation  
Pipelined data output capability  
High-speed access time: 4.5/5/6 nS (max.)  
Single +3.3V power supply  
Supports snooze mode (low-power state)  
Internal burst counter supports Intel burst  
(Interleaved) mode & linear burst mode  
Individual byte write capability  
3.3V LVTTL compatible I/O  
·
·
Support 2T/1T mode  
Clock-controlled and registered input  
Asynchronous output enable  
Packaged in 128-pin QFP and TQFP  
BLOCK DIAGRAM  
INPUT  
A(15:0)  
REGISTER  
64K X 64  
CORE  
ARRAY  
CLK  
CE(3:1)  
GW  
BWE  
CONTROL  
LOGIC  
BW(8:1)  
DATA I/O  
REGISTER  
I/O(64:1)  
REGISTER  
OE  
ADSC  
ADSP  
ADV  
LBO  
ZZ  
Publication Release Date: August 1999  
Revision A3  
- 1 -  

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