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W156CH

更新时间: 2024-11-21 19:58:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
14页 158K
描述
Processor Specific Clock Generator, 124MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

W156CH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:124 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大压摆率:420 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W156CH 数据手册

 浏览型号W156CH的Datasheet PDF文件第2页浏览型号W156CH的Datasheet PDF文件第3页浏览型号W156CH的Datasheet PDF文件第4页浏览型号W156CH的Datasheet PDF文件第5页浏览型号W156CH的Datasheet PDF文件第6页浏览型号W156CH的Datasheet PDF文件第7页 
PRELIMINARY  
W156C  
Spread Spectrum FTG for VIA MVP4  
Features  
Table 1. Mode Input Table  
Mode  
Pin 3  
PCI_STOP#  
REF0  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
• Single-chip implementation  
0
1
• Four copies of CPU output  
• Six copies of PCI output  
• One 48-MHz output for USB  
• One 24-MHz output for SIO  
Table 2. Pin Selectable Frequency  
Input Address  
CPU, SDRAM  
PCI_F, 1:5  
(MHz)  
FS3 FS2 FS1 FS0  
(MHz)  
• Two buffered reference outputs  
• Thirteen SDRAM outputs provide support for 3 DIMMs  
• Supports frequencies up to 124 MHz  
• I2C™ interface for programming  
• Power management control inputs  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
60  
30 (CPU/2)  
66.8  
70  
33.4 (CPU/2)  
35 (CPU/2)  
75  
25 (CPU/3)  
97  
32.3 (CPU/3)  
27.7 (CPU/3)  
31.75 (CPU/3)  
33.3 (CPU/3)  
37.5 (CPU/2)  
32.0 (CPU/3)  
41.7 (CPU/2)  
35 (CPU/3)  
Key Specifications  
83.3  
95.25  
100  
75  
CPU Cycle-to-Cycle Jitter:.......................................... 250 ps  
CPU to CPU Output Skew:......................................... 300 ps  
CPU to PCI Output Skew:.................................. 1.5 to 4.0 ns  
PCI to PCI Output Skew: ............................................ 500 ps  
VDDQ3 = VDDQ_CPU =.............................................. 3.3V±5%  
SDRAMIN to SDRAM0:11 Delay: ..........................4.7 ns typ.  
SDRAM0:11 (leads) to SDRAM_F Skew ...............0.4 ns typ.  
96.2  
83.3  
105  
110  
115  
120  
124  
36.7 (CPU/3)  
38.3 (CPU/3)  
40 (CPU/3)  
41.3 (CPU/3)  
[1, 2]  
Logic Block Diagram  
Pin Configuration  
VDDQ3  
VDDQ3  
REF0/(PCI_STOP#)*  
GND  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF1/FS2*  
1
REF0/(PCI_STOP#)  
REF1/FS2  
VDDQ_CPU  
CPU_F  
2
3
X1  
X2  
OSC  
X1  
CPU1  
4
X2  
5
GND  
PLL Ref Freq  
VDDQ3  
PCI_F/MODE*  
PCI1/FS3*  
GND  
6
CPU2  
CPU3  
7
I/O Pin  
Control  
8
CLK_STOP#*  
GND  
9
PCI2  
SDRAM_F  
SDRAM0  
SDRAM1  
VDDQ3  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
VDDQ3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PCI3  
CLK_STOP#  
PCI4  
VDDQ_CPU  
CPU1:3  
PCI5  
VDDQ3  
SDRAMIN  
GND  
CPU_F  
VDDQ3  
SDRAM11  
SDRAM10  
VDDQ3  
SDRAM9  
SDRAM8  
GND  
÷2,3  
PCI_F/MODE  
PCI1/FS3  
PCI2  
I2C  
{
SDATA  
48MHz/FS0*  
24MHz/FS1*  
PCI3  
SCLK  
PCI4  
2
SDATA  
SCLK  
I C  
PCI5  
Notes:  
Logic  
VDDQ3  
1. Internal pull-up resistors of 250 kto 3.3V present on inputs indicated  
with *.  
48MHz/FS0  
2. Internal pull-up resistors should not be relied upon for setting I/O pins  
HIGH. Pin function with parentheses determined by MODE pin resistor  
strapping.  
÷2  
24MHz/FS1  
VDDQ3  
Stop  
Clock  
Control  
SDRAMIN  
SDRAM0:11  
12  
SDRAM_F  
I2C is a trademark of Philips Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07179 Rev. *A  
Revised December 21, 2002  

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