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W158

更新时间: 2024-11-09 03:18:07
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
12页 220K
描述
Spread Spectrum System Frequency Synthesizer

W158 数据手册

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W158  
W158  
Spread Spectrum System Frequency Synthesizer  
...............................................................................................  
VDDQ2 = 2.5V 5%  
Features  
• Maximized EMI suppression using Cypress’s spread  
spectrum technology  
CPU Output Jitter: ......................................................150 ps  
CPUdiv2, IOAPIC Output Jitter: ..................................250 ps  
48 MHz, 3V66, PCI Output Jitter:................................500 ps  
CPU0:3, CPUdiv2_ 0:1 Output Skew:.........................175 ps  
PCI_F, PCI1:7 Output Skew:.......................................500 ps  
3V66_0:3, IOAPIC0:2 Output Skew: ...........................250 ps  
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)  
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)  
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)  
CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads)  
• Intel® CK98 Specification compliant  
• 0.5% downspread outputs deliver up to 10 dB lower EMI  
• Four skew-controlled copies of CPU output  
• EightcopiesofPCIoutput(synchronousw/CPUoutput)  
• Four copies of 66 MHz fixed frequency 3.3V clock  
• Two copies of CPU/2 outputs for synchronous memory  
reference  
• Three copies of 16.67 MHz IOAPIC clock, synchronous  
to CPU clock  
• One copy of 48 MHz USB output  
Logic inputs, except SEL133/100#, have 250-k: pull-up  
resistors  
Table 1. Pin Selectable Frequency[1]  
• Two copies of 14.31818 MHz reference clock  
• Programmable to 133- or 100-MHz operation  
SEL133/100#  
CPU0:3 (MHz)  
133 MHz  
PCI  
• Power management control pins for clock stop and  
shut down  
1
0
33.3 MHz  
33.3 MHz  
100 MHz  
• Available in 56-pin SSOP  
Note:  
1. See Table 2 for complete mode selection details.  
Key Specifications  
Supply Voltages: ...................................... VDDQ3 = 3.3V 5%  
Block Diagram  
Pin Configuration  
2
X1  
XTAL  
OSC  
REF0:1  
GND  
REF0  
REF1  
VDDQ3  
X1  
X2  
GND  
PCI_F  
PCI1  
VDDQ3  
PCI2  
PCI3  
GND  
PCI4  
PCI5  
VDDQ3  
PCI6  
PCI7  
GND  
GND  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDDQ2  
IOAPIC2  
IOAPIC1  
IOAPIC0  
GND  
VDDQ2  
CPUdiv2_1  
CPUdiv2_0  
GND  
1
2
3
4
5
6
7
8
X2  
CPU_STOP#  
STOP  
Clock  
Logic  
4
2
CPU0:3  
9
VDDQ2  
CPU3  
CPU2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
÷2  
CPUdiv2_0:1  
3V66_0:3  
SPREAD#  
SEL0  
PLL 1  
SEL1  
GND  
STOP  
Clock  
Logic  
4
SEL133/100#  
VDDQ2  
CPU1  
CPU0  
GND  
VDDQ3  
GND  
PCI_STOP#  
CPU_STOP#  
PWRDWN#  
SPREAD#  
SEL1  
÷2/÷1.5  
1
7
PCI_F  
PCI1:7  
STOP  
Clock  
Logic  
3V66_0  
3V66_1  
VDDQ3  
GND  
3V66_2  
3V66_3  
VDDQ3  
÷2  
PWRDWN#  
PCI_STOP#  
SEL0  
25  
26  
27  
28  
3
VDDQ3  
48MHz  
GND  
Power  
Down  
Logic  
÷2  
IOAPIC0:2  
SEL133/100#  
Three-state  
Logic  
1
PLL2  
48MHz  
Rev 1.0, November 21, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 12  
www.SpectraLinear.com  
Tel:(408) 855-0555 Fax:(408) 855-0550  

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