VSC9295
Datasheet
TABLES
Table 1. I/O Sizing Modes ..........................................................................................................................23
Table 2. Interrupt Source Bit Allocation ......................................................................................................31
Table 3. Bitslicer Modes .............................................................................................................................42
Table 4. JTAG External I/O Signals ............................................................................................................43
Table 5. Boundary Scan Test Instructions ..................................................................................................44
Table 6. Test Instruction Descriptions .........................................................................................................45
Table 7. Device ID Register Table ..............................................................................................................45
Table 8. TAP Controller State Descriptions ................................................................................................47
Table 9. Bitslice and Size Controls .............................................................................................................50
Table 10. Register Bank Mapping for Non-Bitsliced (BS1) and 4x Bit-Sliced (BS4) Modes ........................51
Table 11. Register Bank Mapping by TSI Mode for 2x Bit-Sliced (BS2) Modes ..........................................52
Table 12. Code Setting and Domain for Functions .....................................................................................54
Table 13. SFG Block Outputs .....................................................................................................................54
Table 14. Values for Jitter Tolerance Mask .................................................................................................64
Table 15. Lock Detector Tolerance Settings ...............................................................................................66
Table 16. RXEQCTRL Settings ..................................................................................................................67
Table 17. LOS Threshold Settings .............................................................................................................68
Table 18. Drive and Pre-Emphasis Settings ...............................................................................................70
Table 19. VSC9295 Memory Map ..............................................................................................................73
Table 20. TSI Register Map ........................................................................................................................78
Table 21. TSI Register Map Signals ...........................................................................................................99
Table 22. BPRx Register Map ..................................................................................................................100
Table 23. BPRx Register Map Signals .....................................................................................................102
Table 24. BPTx Register Map ..................................................................................................................105
Table 25. BPTx Register Map Signals ......................................................................................................110
Table 26. SFG Register Map ....................................................................................................................113
Table 27. SFG Register Map R/W Control Bits .........................................................................................113
Table 28. SyncMan Register Map ............................................................................................................114
Table 29. SyncMan Register Map Signals ................................................................................................114
Table 30. PLL Controls Register Map .......................................................................................................116
Table 31. PLL Controls Register Map Signals ..........................................................................................116
Table 32. PLL Status Register Map ..........................................................................................................117
Table 33. PLL Status Register Map Signals .............................................................................................117
Table 34. Test Control Register Map ........................................................................................................118
Table 35. Test Control Register Map Signals ...........................................................................................118
9 of 157
VMDS-10144 Revision 4.4
April 2009
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