VSC9295
Datasheet
FIGURES
Figure 1. VSC9295 Block Diagram ..............................................................................................................2
Figure 2. VSC9295 Used as a Working Switch in a Monolithic Application (340 Gb) .................................13
Figure 3. VSC9295 Used as a Working Switch in a Bitslicing Application (680 Gb) ...................................14
Figure 4. TFI-5/SONET/SDH Frame Format ..............................................................................................18
Figure 5. The VSC9295 Short Frame Format ............................................................................................19
Figure 6. STS-12/STM-4 Frame Format ....................................................................................................20
Figure 7. Four-Way Bitslicing (Slicing into 2-Bit Units) ...............................................................................23
Figure 8. Four VSC9295s in Parallel Performing Bit Pair-Level Switching .................................................24
Figure 9. Deslicing a 4-Way Bitsliced Data Stream ....................................................................................24
Figure 10. 8-Way Bitslicing Operation (Slicing into 1-Bit Units) ..................................................................25
Figure 11. 680 Gbps Switch Fabric Application .........................................................................................25
Figure 12. Example 1.36 Tbps Fabric Configuration .................................................................................26
Figure 13. 680 Gbps Switch Fabric with Protection Plane .........................................................................27
Figure 14. Cascading Multiple VSC9295 Devices ......................................................................................27
Figure 15. Timing of newcfg and FSYNC in Cascaded Applications ..........................................................28
Figure 16. VSC9295 CPU Interface Block Diagram ...................................................................................30
Figure 17. SyncMan Block Diagram ...........................................................................................................34
Figure 18. Frame Sync Position with BPOFFSET ......................................................................................35
Figure 19. Frame Sync Position with BPOFFSET Adjusted for Worst-Case Skew (STS-48 Mode) ...........36
Figure 20. Summary of Overhead Monitor/Insertion Bytes ........................................................................37
Figure 21. Format of BPIxROW, BPIxCOL .................................................................................................38
Figure 22. Overhead Monitoring Interface Timing for Dropping Bytes to ohdataout ...................................40
Figure 23. Overhead Monitoring Interface Timing for Accepting Bytes at ohdatain[7:0] .............................40
Figure 24. Bitslicer Block Diagram .............................................................................................................41
Figure 25. Boundary Scan Test Architecture ..............................................................................................44
Figure 26. TAP Controller State Diagram ...................................................................................................46
Figure 27. Block Diagram of a Single TSI Slice (One of 68) .......................................................................48
Figure 28. BPRx Block Diagram ................................................................................................................56
Figure 29. BPTx Block Diagram .................................................................................................................60
Figure 30. Data Sampling Diagram ............................................................................................................63
Figure 31. Jitter Transfer Mask ...................................................................................................................64
Figure 32. Jitter Tolerance Mask ................................................................................................................65
Figure 33. Backplane Receiver Multiplexer Function at 2.5 Gbps ..............................................................66
Figure 34. Backplane Transmitter Multiplexer Function at 2.5 Gbps ..........................................................69
Figure 35. High-Speed Level Definitions ..................................................................................................124
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VMDS-10144 Revision 4.4
April 2009
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