VSC9295
Datasheet
2.2.1 Variable Frame Length....................................................................................................... 34
2.2.2 Split Frame Domains.......................................................................................................... 35
2.2.3 Framesync Filtering—Filter Window................................................................................... 35
2.2.4 Sync Offset Control ............................................................................................................ 35
2.3 Overhead Monitor and Insertion ........................................................................................................37
2.3.1 Transmit Side Custom Overhead Insertion ........................................................................ 37
2.3.2 Extended Custom Overhead Insertion ............................................................................... 38
2.3.3 Extra Extended Custom Overhead Insertion...................................................................... 39
2.3.4 Backplane Receiver Side Overhead Monitoring................................................................. 39
2.3.5 Overhead Monitor Interface................................................................................................ 39
2.4 Static Bitslicing Block .........................................................................................................................41
2.4.1 Bitslicing Modes and Bit Pair Select Mode......................................................................... 42
2.5 JTAG ..................................................................................................................................................42
2.5.1 JTAG Boundary Scan Input/Output.................................................................................... 43
2.5.2 Boundary Scan Testing ...................................................................................................... 43
2.5.3 Instruction Register............................................................................................................. 44
2.5.4 Supported Test Instructions................................................................................................ 45
2.5.5 Device ID Register.............................................................................................................. 45
2.5.6 Bypass Register ................................................................................................................. 45
2.5.7 Boundary Scan Register..................................................................................................... 46
2.5.8 TAP Controller.................................................................................................................... 46
2.6 Clock Multiplier ..................................................................................................................................48
2.7 TSI Switch Core (TSI) ........................................................................................................................48
2.7.1 Hitless Switching ................................................................................................................ 49
2.7.2 Broadcast and Multicast ..................................................................................................... 49
2.7.3 STS-1 Switching................................................................................................................. 49
2.7.4 Bitslicing ............................................................................................................................. 49
2.7.5 Transparent Mode .............................................................................................................. 50
2.7.6 Connection Provisioning..................................................................................................... 50
2.7.7 Transparent Mode Provisioning.......................................................................................... 53
2.7.8 Path AIS and UNEQ Insertion ............................................................................................ 53
2.7.9 Generated Pattern Insertion ............................................................................................... 54
2.7.10 TSI Configuration Change................................................................................................ 55
2.7.11 Memory Integrity Check.................................................................................................... 55
2.7.12 Reset State....................................................................................................................... 56
2.8 Low-Speed Backplane Receiver .......................................................................................................56
2.8.1 Frame Formats................................................................................................................... 57
2.8.2 Out-of-Frame Detection (OOF)........................................................................................... 57
2.8.3 Frame Offset Detection ...................................................................................................... 57
2.8.4 Elastic Store ....................................................................................................................... 57
2.8.5 Out-Of-Alignment (OOA) Detection.................................................................................... 58
2.8.6 Transparent Mode .............................................................................................................. 58
2.8.7 Section Error Monitoring (B1)............................................................................................. 58
2.8.8 De-Scrambling.................................................................................................................... 58
2.8.9 LOS Detection .................................................................................................................... 58
2.8.10 Unequipped Port............................................................................................................... 59
2.8.11 AIS Insertion..................................................................................................................... 59
2.8.12 HSIRx Control and Monitoring.......................................................................................... 59
2.9 Low-Speed Backplane Transmitter ...................................................................................................59
4 of 157
VMDS-10144 Revision 4.4
April 2009
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