VSC9295
Datasheet
CONTENTS
1 Product Overview ...........................................................................................................13
1.1 Interconnection Matrix .......................................................................................................................14
1.1.1 STS-1 Switching................................................................................................................. 14
1.2 Input Backplane Interface ..................................................................................................................15
1.3 Output Backplane Interface ...............................................................................................................15
1.4 Other Ports ........................................................................................................................................16
1.4.1 Overhead Monitor Port ....................................................................................................... 16
1.4.2 CPU Interface..................................................................................................................... 16
1.4.3 Test Interface...................................................................................................................... 16
1.4.4 Clock Synthesis for Phase-Locked Loop............................................................................ 16
1.5 Data Formats .....................................................................................................................................17
1.5.1 TFI-5 Mode (TFI-5, SONET, and SDH Frames)................................................................. 17
1.5.2 Short Frame Mode.............................................................................................................. 19
1.5.3 STS-12 / STM-4 SONET / SDH Frames ............................................................................ 19
1.5.4 Transparent Mode .............................................................................................................. 21
1.6 Miscellaneous Functions ...................................................................................................................21
1.6.1 Frame Synchronization....................................................................................................... 21
1.6.2 Internal Frame Distribution ................................................................................................. 21
1.6.3 Dual Frame Domains.......................................................................................................... 22
1.6.4 Bitslicing and Sizing............................................................................................................ 22
1.7 Application Information ......................................................................................................................25
1.7.1 Expandability ...................................................................................................................... 25
1.7.2 Protection Plane Schemes ................................................................................................. 26
1.7.3 Cascading Multiple Devices ............................................................................................... 27
2 Functional Descriptions .................................................................................................29
2.1 CPU Interface ....................................................................................................................................29
2.1.1 Asynchronous Interfaces.................................................................................................... 30
2.1.2 Memory Paging .................................................................................................................. 30
2.1.3 Writing Individual Register Bits........................................................................................... 30
2.1.4 Interrupt Generation ........................................................................................................... 31
2.1.5 Device Reset Control.......................................................................................................... 31
2.1.6 General Configuration Registers ........................................................................................ 31
2.1.7 PLL Monitoring ................................................................................................................... 32
2.1.8 PLL Control......................................................................................................................... 32
2.1.9 Switch Configuration Request ............................................................................................ 32
2.1.10 Test Control...................................................................................................................... 32
2.1.11 Multiple Interface Modes .................................................................................................. 33
2.1.12 Intel Non-Multiplexed Mode.............................................................................................. 33
2.1.13 Multiplexed Mode, Read and Write .................................................................................. 33
2.1.14 Motorola Mode.................................................................................................................. 33
2.2 Frame Synchronization Manager ......................................................................................................34
3 of 157
VMDS-10144 Revision 4.4
April 2009