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VP1509NJ PDF预览

VP1509NJ

更新时间: 2024-10-29 13:15:31
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
2页 334K
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VP1509NJ 数据手册

 浏览型号VP1509NJ的Datasheet PDF文件第2页 
VP1504/VP1506/VP1509  
P-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
BVDSS  
/
RDS(ON)  
ID(ON)  
BVDGS  
(max)  
(min)  
Die†  
-40V  
8.0Ω  
8.0Ω  
8.0Ω  
-0.5A  
VP1504NW  
-60V  
-0.5A  
-0.5A  
VP1506NW  
VP1509NW  
-90V  
† MIL visual screening available.  
Features  
Advanced DMOS Technology  
Free from secondary breakdown  
Low power drive requirement  
Ease of paralleling  
This enhancement-mode (normally-off) transistor utilizes a  
vertical DMOS structure and Supertex’s well-proven silicon-gate  
manufacturing process. This combination produces adevice with  
the power handling capabilities of bipolar transistors and with the  
high input impedance and positive temperature coefficient inher-  
ent in MOS devices. Characteristic of all MOS structures, this  
device is free from thermal runaway and thermally-induced  
secondary breakdown.  
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral Source-Drain diode  
High input impedance and high gain  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where high breakdown  
voltage, high input impedance, low input capacitance, and fast  
switching speeds are desired.  
Complementary N- and P-channel devices  
Applications  
Motor controls  
Converters  
Amplifiers  
Switches  
Power supply circuits  
Drivers (relays, hammers, solenoids, lamps, memories,  
displays, bipolar transistors, etc.)  
Absolute Maximum Ratings  
Drain-to-Source Voltage  
Drain-to-Gate Voltage  
Gate-to-Source Voltage  
BVDSS  
BVDGS  
±±0V  
Operating and Storage Temperature  
-55OC to +150OC  
300OC  
Soldering Temperature*  
* Distance of 1.6 mm from case for 10 seconds.  
1

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