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VP16256-27/CG/GH1N PDF预览

VP16256-27/CG/GH1N

更新时间: 2024-11-25 03:19:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK DSP外围设备微控制器和处理器外围集成电路LTE时钟
页数 文件大小 规格书
19页 459K
描述
Programmable FIR FIlter

VP16256-27/CG/GH1N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:QFP, QFP208,1.2SQ,20Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
边界扫描:NO最大时钟频率:27 MHz
外部数据总线宽度:16JESD-30 代码:S-PQFP-G208
JESD-609代码:e0低功率模式:NO
端子数量:208最高工作温度:70 °C
最低工作温度:输出数据总线宽度:16
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
子类别:DSP Peripherals最大压摆率:325 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIEDuPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches:1

VP16256-27/CG/GH1N 数据手册

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VP16256  
Programmable FIR FIlter  
Advance Information  
DS4548  
ISSUE 4.0  
August 1998  
The VP16256 contains sixteen multiplier - accumulators, which  
canbemulticycledtoprovidefrom16to128stagesofdigitalfiltering.  
Input data and coefficients are both represented by 16-bit two’s  
complementnumberswithcoefficientsconvertedinternallyto12bits  
and the results being accumulated up to 32 bits.  
PIN 1  
In16-tapmodethedevicesamplesdataatthesystemclockrate  
ofupto40MHz. Ifalowersamplerateisacceptablethenthenumber  
ofstagescanbeincreasedinpowersoftwouptoamaximumof128.  
Each time the number of stages is doubled, the sample clock rate  
mustbehalvedwithrespecttothesystemclock. With128stagesthe  
sample clock is therefore one eighth of the system clock.  
In all speed modes devices can be cascaded to provide filters of  
anylength,onlylimitedbythepossibilityofaccumulatoroverflow.The  
32-bit results are passed between cascaded devices without any  
intermediate scaling and subsequent loss of precision.  
PIN 1 IDENT  
PIN  
208  
The device can be configured as either one long filter or two  
separate filters with half the number of taps in each. Both networks  
can have independent inputs and outputs.  
Bothsingleandcascadeddevicescanbeoperatedindecimate-  
by-two mode. The output rate is then half the input rate, but twice the  
numberofstagesarepossibleatagivensamplerate.Asingledevice  
witha40MHzclockwouldthen,forexample,providea128-stagelow  
pass filter, with a 10MHz input rate and 5MHz output rate.  
Coefficients are stored internally and can be down loaded from  
a host system or an EPROM. The latter requires no additional  
support, and is used in stand alone applications. A full set of  
coefficientsisthenautomaticallyloadedatpoweron,orattherequest  
of the system. A single EPROM can be used to provide coefficients  
for up to 16 devices.  
GH208  
Pin identification diagram (top view)  
See Table 1 for pin descriptions and Table 2 for pinout  
FEATURES  
I Sixteen MACs in a Single Device  
I Basic Mode is 16-Tap Filter at up to 40MHz  
Sample Rates  
CHANGE  
EPROM  
COEFF  
ADDR DATA  
POWER-ON  
RESET  
I Programmable to give up to 128 Taps with  
Sampling Rates Proportionally Reducing to 5MHz  
I 16-bit Data and 32-bit Accumulators  
I Can be configured as One Long Filter or Two Half-  
Length Filters  
RES  
VP  
16256  
INPUT  
DATA  
OUTPUT  
DATA  
I Decimate-by-two Option will Double the Filter  
Length  
I Coefficients supplied from a Host System or a local  
EPROM  
EPROM  
SCLK  
GND  
Fig. 1 A dual filter application  
I 208-Pin Plastic PowerQuad PQ2 Package  
CHANGE  
EPROM  
COEFF  
ADDR DATA  
POWER-ON  
RESET  
APPLICATIONS  
I High Performance Commercial Digital Filters  
I Matrix Multiplication  
RES  
COEFFICIENTS  
I Correlation  
I High Performance Adaptive Filtering  
VP  
16256  
ANALOG  
INPUT  
OUTPUT  
DATA  
ADC  
ORDERING INFORMATION  
VP16256-27/CG/GH1N 27MHz, Commercial plastic  
PowerQuad PQ2 package (GH208)  
VP16256-40/CG/GH1N 40MHz, Commercial plastic  
PowerQuad PQ2 package (GH208)  
EPROM  
GND  
CLKOP  
SCLK  
Fig. 2 Typical system application  

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