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VP16256-27 PDF预览

VP16256-27

更新时间: 2024-11-20 22:36:47
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MITEL /
页数 文件大小 规格书
20页 230K
描述
Programmable FIR Filter

VP16256-27 数据手册

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VP16256  
Programmable FIR Filter  
Advance Information  
Supersedes August 1997 version, DS4548 - 3.2  
DS4548 - 4.0 August 1998  
The VP16256 contains sixteen multiplier - accumulators, which  
canbemulticycledtoprovidefrom16to128stagesofdigitalfiltering.  
Input data and coefficients are both represented by 16-bit two’s  
complementnumberswithcoefficientsconvertedinternallyto12bits  
and the results being accumulated up to 32 bits.  
PIN 1  
In16-tapmodethedevicesamplesdataatthesystemclockrate  
ofupto40MHz. Ifalowersamplerateisacceptablethenthenumber  
ofstagescanbeincreasedinpowersoftwouptoamaximumof128.  
Each time the number of stages is doubled, the sample clock rate  
mustbehalvedwithrespecttothesystemclock.With128stagesthe  
sample clock is therefore one eighth of the system clock.  
In all speed modes devices can be cascaded to provide filters of  
anylength,onlylimitedbythepossibilityofaccumulatoroverflow.The  
32-bit results are passed between cascaded devices without any  
intermediate scaling and subsequent loss of precision.  
PIN 1 IDENT  
PIN  
208  
The device can be configured as either one long filter or two  
separate filters with half the number of taps in each. Both networks  
can have independent inputs and outputs.  
Bothsingleandcascadeddevicescanbeoperatedindecimate-  
by-two mode. The output rate is then half the input rate, but twice the  
numberofstagesarepossibleatagivensamplerate.Asingledevice  
witha40MHzclockwouldthen,forexample,providea128-stagelow  
pass filter, with a 10MHz input rate and 5MHz output rate.  
Coefficients are stored internally and can be down loaded from  
a host system or an EPROM. The latter requires no additional  
support, and is used in stand alone applications. A full set of  
coefficientsisthenautomaticallyloadedatpoweron,orattherequest  
of the system. A single EPROM can be used to provide coefficients  
for up to 16 devices.  
GH208  
Pin identification diagram (top view)  
See Table 1 for pin descriptions and Table 2 for pinout  
FEATURES  
Sixteen MACs in a Single Device  
Basic Mode is 16-Tap Filter at up to 40MHz  
Sample Rates  
CHANGE  
EPROM  
COEFF  
ADDR DATA  
POWER-ON  
RESET  
Programmable to give up to 128 Taps with  
Sampling Rates Proportionally Reducing to 5MHz  
16-bit Data and 32-bit Accumulators  
Can be configured as One Long Filter or Two Half-  
Length Filters  
RES  
VP  
16256  
INPUT  
DATA  
OUTPUT  
DATA  
Decimate-by-two Option will Double the Filter  
Length  
Coefficients supplied from a Host System or a local  
EPROM  
EPROM  
SCLK  
GND  
Fig. 1 A dual filter application  
208-Pin Plastic PowerQuad PQ2 Package  
CHANGE  
EPROM  
COEFF  
ADDR DATA  
POWER-ON  
RESET  
APPLICATIONS  
High Performance Commercial Digital Filters  
Matrix Multiplication  
RES  
COEFFICIENTS  
Correlation  
VP  
16256  
High Performance Adaptive Filtering  
ANALOG  
INPUT  
OUTPUT  
DATA  
ADC  
ORDERING INFORMATION  
VP16256-27/CG/GH1N 27MHz, Commercial plastic  
PowerQuad PQ2 package (GH208)  
EPROM  
GND  
CLKOP  
SCLK  
VP16256-40/CG/GH1N 40MHz, Commercial plastic  
PowerQuad PQ2 package (GH208)  
Fig. 2 Typical system application  

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