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VIRTEX-4

更新时间: 2024-09-17 03:19:59
品牌 Logo 应用领域
赛灵思 - XILINX 以太网
页数 文件大小 规格书
9页 195K
描述
Tri-Mode Embedded Ethernet MAC Wrapper v4.4

VIRTEX-4 数据手册

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Virtex-4 Tri-Mode Embedded  
Ethernet MAC Wrapper v4.4  
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DS307 February 15, 2007  
Product Specification  
Introduction  
LogiCORE Facts  
Supported Family  
Virtex-4 FX  
The LogiCORE™ Virtex-4™ Embedded Tri-Mode  
Ethernet Media Access Controller (MAC) Wrapper  
automates the generation of HDL wrapper files for the  
Tri-Mode Ethernet MAC in Virtex-4 FX devices using  
the Xilinx CORE Generator™.  
Performance  
10 Mbps, 100 Mbps, 1 Gbps  
Example Design Resources  
Slices  
LUTs  
366-11121  
1
420-1233  
1
FFs  
432-1355  
VHDL and Verilog instantiation templates are available  
in the Libraries Guide for the Virtex-4 Ethernet MAC  
primitive; however, due to the complexity and the large  
number of ports, the CORE Generator simplifies inte-  
gration of the Ethernet MAC by providing HDL exam-  
ples based on user-selectable configurations.  
1
Block RAMs  
DCM  
4-8  
1
0-2  
1
BUFG  
2-8  
Wrapper Highlights  
Optimized Clocking Logic  
Hardware Verified  
HDL Example Design  
Demonstration Test Bench  
Provided with Wrapper  
Features  
• Allows selection of one or both Ethernet MACs  
(EMAC0/EMAC1) from the Embedded Ethernet  
MAC primitive  
Documentation  
Product Specification  
Getting Started Guide  
User Guide2  
Design File Formats  
HDL Example Design,  
Demonstration Test Bench, Scripts  
• Connects the EMAC0/EMAC1 tie-off pins based on  
user options  
Constraints File  
User Constraints File (UCF)  
Example FIFO connected to client I/F  
Demonstration Test Environment  
Example Designs  
• Provides user-configurable Ethernet MAC physical  
interfaces, including  
Design Tool Requirements  
- Supports MII, GMII, RGMII v1.3, RGMII v2.0,  
SGMII, and 1000BASE-X PCS/PMA interfaces  
Supported HDL  
Synthesis  
VHDL and/or Verilog  
XST 9.1i  
Xilinx Tools  
ISE™ 9.1i  
- Instantiates clock buffers, DCMs, RocketIO™  
Multi-Gigabit Transceivers (MGTs), and logic as  
required for the selected physical interfaces  
Simulation Tools  
(SWIFT-compliant  
simulator required)  
Mentor ModelSim® 6.1e  
Cadence™ IUS3  
• Provides a simple FIFO-loopback example design,  
which is connected to the MAC client interfaces  
1. The precise number depends on user configuration; see "Device  
Utilization" on page 7.  
2. The Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide is  
available under the Related Information area of the product page.  
3. Scripts provided for Mentor ModelSim and Cadence IUS only.  
• Provides a simple demonstration test bench based  
on the selected configuration  
• Includes an example of a low-level driver for DCR  
accesses  
• Generates VHDL or Verilog  
© 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective  
owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx  
makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly  
disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims  
of infringement and any implied warranties of merchantability or fitness for a particular purpose.  
DS307 February 15, 2007  
www.xilinx.com  
1
Product Specification  

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