5秒后页面跳转
捷配首页

Datasheet > VIRTEX-II
VIRTEX-II PDF预览

VIRTEX-II

更新时间： 2024-09-16 23:44:35
品牌 Logo 应用领域
其他 - ETC 现场可编程门阵列栅
页数 文件大小 规格书
7页 128K
描述
1.5V Field-Programmable Gate Arrays

阅读下载

中文翻译

获取价格

VIRTEX-II 数据手册

 浏览型号VIRTEX-II的Datasheet PDF文件第2页浏览型号VIRTEX-II的Datasheet PDF文件第3页浏览型号VIRTEX-II的Datasheet PDF文件第4页浏览型号VIRTEX-II的Datasheet PDF文件第5页浏览型号VIRTEX-II的Datasheet PDF文件第6页浏览型号VIRTEX-II的Datasheet PDF文件第7页 
0
R
Virtex-II 1.5V  
Field-Programmable Gate Arrays  
0
0
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
®
Summary of Virtex -II Features  
•
Industry First Platform FPGA Solution  
-
-
-
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
•
IP-Immersion™ Architecture  
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz  
compliance, and CardBus compliant  
-
-
-
Densities from 40K to 8M system gates  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
Differential Signaling  
·
840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
•
SelectRAM™ Memory Hierarchy  
-
3 Mb of True Dual-Port™ RAM in 18-Kbit block  
SelectRAM resources  
·
·
-
-
Up to 1.5 Mb of distributed SelectRAM resources  
High-performance interfaces to external memory  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
·
·
·
·
DDR-SDRAM interface  
FCRAM interface  
QDR™-SRAM interface  
Sigma RAM interface  
·
Built-in DDR Input and Output registers  
-
Proprietary high-performance SelectLink™  
Technology  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
•
•
Arithmetic Functions  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
•
•
Supported by Xilinx Foundation™ and Alliance™  
Series Development Systems  
Flexible Logic Resources  
-
Up to 93,184 internal registers / latches with Clock  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Enable  
-
Up to 93,184 look-up tables (LUTs) or cascadable  
16-bit shift registers  
SRAM-Based In-System Configuration  
-
-
Wide multiplexers and wide-input function support  
-
-
Fast SelectMAP™ configuration  
Horizontal cascade chain and Sum-of-Products  
support  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
-
Internal 3-state bussing  
-
-
-
-
IEEE1532 support  
•
High-Performance Clock Management Circuitry  
Partial reconfiguration  
Unlimited re-programmability  
Readback capability  
-
Up to 12 DCM (Digital Clock Manager) modules  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
•
•
0.15 µm 8-Layer Metal process with 0.12 µm  
high-speed transistors  
-
16 global clock multiplexer buffers  
1.5 V (VCCINT) core power supply, dedicated 3.3 V  
CCAUX auxiliary and VCCO I/O power supplies  
•
•
Active Interconnect™ Technology  
V
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
•
•
IEEE 1149.1 compatible boundary-scan logic support  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
packages in three standard fine pitches (0.80mm,  
1.00mm, and 1.27mm)  
SelectI/O-Ultra™ Technology  
-
-
Up to 1,108 user I/Os  
19 single-ended standards and six differential  
standards  
•
100% factory tested  
-
Programmable sink current (2 mA to 24 mA) per I/O  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
1234567

中文翻译

下载PDF

与VIRTEX-II相关器件

型号 品牌 获取价格 描述 数据表
VIRTEXQPRO ETC

获取价格

 		QPro Virtex 2.5V QML High-Reliability FPGAs
VI-RTL01-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL03-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL0L-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL0M-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL0Z-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL10-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL14-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL1L-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,
VI-RTL1M-XXXX VICOR

获取价格

 		DC-DC Regulated Power Supply Module, 3 Output,

与VIRTEX-II相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证