Datasheet > V62/08613-01XE

V62/08613-01XE

更新时间： 2024-11-04 12:21:51

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
12页	600K
描述
DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

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V62/08613-01XE 数据手册

SN74HC74-EP

DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP

WITH CLEAR AND PRESET

www.ti.com

SCLS710–MARCH 2008

FEATURES

•

Controlled Baseline

•

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive up to 10 LSTTL Loads

Low Power Consumption, 80 µA Max I_CC

Typical t_pd= 15 ns

–

One Assembly Site

One Test Site

One Fabrication Site

•

Extended Temperature Performance of –55°C

to 125°C

±4 mA Output Drive at 5 V

Low Input Current of 1 mA Max

Enhanced Diminishing Manufacturing Sources

(DMS) Support

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

The SN74HC74 device contains two independent D-type positive edge triggered flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred

to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed

without affecting the levels at the outputs.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

Reel of 2500

Reel of 2000

ODERABLE PART NUMBER

SN74HC74MDREP

TOP-SIDE MARKING

HC74MEP

SOIC – D

–55°C to 125°C

TSSOP – PW

SN74HC74MPWREP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE CLR CLK

↑

H⁽¹⁾H⁽¹⁾

↑

Q₀

Q ₀

(1) This configuration is nonstable;

that is, it does not persist when

PRE or CLR returns to its inactive

(high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

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V62/08613-01XE 替代型号

型号	品牌	替代类型	描述	数据表
SN74HC74MPWREP	TI	完全替代	DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

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