Datasheet > 微控制器和处理器 > 串行 IO/通信控制器> V62/08625-01XE

V62/08625-01XE

更新时间： 2024-11-17 11:58:39

品牌	Logo	应用领域
德州仪器 - TI		微控制器和处理器串行IO控制器通信控制器外围集成电路 PC
页数	文件大小	规格书
6页	82K
描述
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER

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V62/08625-01XE 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP, QFP176,1.0SQ,20	针数：	176
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
Factory Lead Time：	6 weeks	风险等级：	5.76
Is Samacsys：	N	地址总线宽度：
边界扫描：	NO	总线兼容性：	PCI
通信协议：	ASYNC, BIT	最大数据传输速率：	50 MBps
外部数据总线宽度：		JESD-30 代码：	S-PQFP-G176
JESD-609代码：	e4	长度：	24 mm
低功率模式：	NO	湿度敏感等级：	3
DMA 通道数量：	5	端子数量：	176
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP176,1.0SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3,5 V	座面最大高度：	1.6 mm
子类别：	Bus Controllers	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	24 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

V62/08625-01XE 数据手册

TSB12LV21B-EP

www.ti.com...................................................................................................................................................................................................... SLLA274–APRIL 2008

(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER

FEATURES

•

Controlled Baseline

•

3.3-V Core Logic While Maintaining

5-V Tolerant Inputs

–

One Assembly Site

One Test Site

•

Performs the Function of 1394 Cycle Master

Provides 4 KBytes of Configurable FIFO RAM

Provides Five Scatter-Gather DMA Channels

Provides Software Control of Interrupt Events

Provides Four General-Purpose Input/Outputs

Supports Plug-and-Play (PnP) Specification

One Fabrication Site

•

Extended Temperature Performance of

–55°C to 125°C

Enhanced Diminishing Manufacturing Sources

(DMS) Support

•

Enhanced Product-Change Notification

Generates 32-Bit CRC for Transmission of

1394 Packets

(1)

Qualification Pedigree

IEEE Standard for 1394-1995 Compliant

IEEE Standard for 1212-1991 Compliant

Supports IEEE 1394-1995 Link Layer Control

•

Performs 32-Bit CRC Checking on Reception

of 1394 Packets

Provides PCI Bus Master Function for

Supporting DMA Operations

PCI Local Bus Specification Rev. 2.1

Compliant

Provides PCI Slave Function for Read/Write

Access of Internal Registers

•

Supports IEEE 1394 Transfer Rates of 100,

200, and 400 Mbit per Second

Supports Distributed DMA Transfers Between

1394 and Local Bus RAM, ROM, AUX, or

Zoomed Video

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

•

Advanced Submicron, Low-Power CMOS

Technology

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

Packaged in a 176-Pin PQFP (PGF)

DESCRIPTION

The TSB12LV21B (PCILynx-2) provides a high-performance IEEE 1394-1995 interface with the capability to

transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to the

local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device; it is

supported by the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving

1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s.

The link layer also provides the capability to receive status from the physical layer device and to access the

physical layer control and status registers by the application software. The PCILynx-2 complies with

•

PCI Local Bus Specification, Revision 2.1

IEEE Standard for a 1394-1995 High Performance Serial Bus

IEEE Standard 1212-1991

IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses

An internal 4 Kbyte memory can be configured as multiple variable-size FIFOs, eliminating the need for external

FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and

isosynchronous transmit transfer operations.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

12 3 4 5 6

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