Datasheet > V53C16256SH

V53C16256SH

更新时间： 2024-09-12 22:16:39

品牌	Logo	应用领域
MOSEL		/
页数	文件大小	规格书
19页	147K
描述
256K X 16 FAST PAGE MODE CMOS DYNAMIC RAM WITH SELF REFRESH

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中文翻译

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数据手册

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V53C16256SH 数据手册

V53C16256SH

PRELIMINARY

MO SEL VITELIC

256K X 16 FAST PAGE MODE

CMOS DYNAMIC RAM WITH

SELF REFRESH

HIGH PERFORMANCE

Max. RAS Access Time, (t

)

40 ns

20 ns

23 ns

75 ns

50 ns

24 ns

28 ns

90 ns

RAC

Max. Column Address Access Time, (t

)

CAA

Min. Fast Page Mode Cycle Time, (t

)

Min. Read/Write Cycle Time, (t

)

Features

Description

■ 256K x 16-bit organization

The V53C16256SH is a 262,144 x 16 bit high-

performance CMOS dynamic random access mem-

ory. The V53C16256SH offers Fast Page mode

with dual CAS inputs. An address, CAS and RAS in-

put capacitances are reduced to one quarter when

the x4 DRAM is used to construct the same memory

density. The V53C16256SH has symmetric ad-

dress and accepts 512 cycle 8ms interval.

■ Fast Page Mode for a sustained data rate

of 43 MHz

■ RAS access time: 40, 50 ns

■ Dual CAS Inputs

■ Low power dissipation

■ Read-Modify-Write, RAS-Only Refresh,

CAS-Before-RAS Refresh, and Self Refresh

■ Refresh Interval: 512 cycles/8 ms

■ Available in 40-pin 400 mil SOJ and

40/44L-pin 400 mil TSOP-II packages

■ Single 5.0V ±10% Power Supply

■ TTL Interface

All inputs are TTL compatible. Fast Page Mode

operation allows random access up to 512 x 16 bits,

within a page, with cycle times as short as 23ns.

The V53C16256SH is best suited for graphics,

and DSP applications.

■ Self Refresh: 512 cycles/8ms

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Power

Std.

•

Temperature

Mark

0°C to 70°C

•

Blank

V53C16256SH Rev. 0.1 December 1998

12 3 4 5 6 7...19

中文翻译

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